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thurstondthurstond
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[msan] Model is_int_min_poison to avoid false negative in abs (#148069)
Note: since this patch reduces false negatives, buggy code that formerly passed with MSan may start failing. The current MSan handler for abs, like Hercules' in New York, ignores is_int_min_poison. This patch fixes the issue by poisoning the shadow corresponding to each int_min input value if is_int_min_poison.
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lines changed

4 files changed

+119
-65
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‎llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp‎

Lines changed: 27 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -4569,16 +4569,37 @@ struct MemorySanitizerVisitor : public InstVisitor<MemorySanitizerVisitor> {
45694569
SC.Done(&I);
45704570
}
45714571

4572-
// Instrument abs intrinsic.
4573-
// handleUnknownIntrinsic can't handle it because of the last
4574-
// is_int_min_poison argument which does not match the result type.
4572+
// Instrument @llvm.abs intrinsic.
4573+
//
4574+
// e.g., i32 @llvm.abs.i32 (i32 <Src>, i1 <is_int_min_poison>)
4575+
// <4 x i32> @llvm.abs.v4i32(<4 x i32> <Src>, i1 <is_int_min_poison>)
45754576
void handleAbsIntrinsic(IntrinsicInst &I) {
4577+
assert(I.arg_size() == 2);
4578+
Value *Src = I.getArgOperand(0);
4579+
Value *IsIntMinPoison = I.getArgOperand(1);
4580+
45764581
assert(I.getType()->isIntOrIntVectorTy());
4577-
assert(I.getArgOperand(0)->getType() == I.getType());
45784582

4579-
// FIXME: Handle is_int_min_poison.
4583+
assert(Src->getType() == I.getType());
4584+
4585+
assert(IsIntMinPoison->getType()->isIntegerTy());
4586+
assert(IsIntMinPoison->getType()->getIntegerBitWidth() == 1);
4587+
45804588
IRBuilder<> IRB(&I);
4581-
setShadow(&I, getShadow(&I, 0));
4589+
Value *SrcShadow = getShadow(Src);
4590+
4591+
APInt MinVal =
4592+
APInt::getSignedMinValue(Src->getType()->getScalarSizeInBits());
4593+
Value *MinValVec = ConstantInt::get(Src->getType(), MinVal);
4594+
Value *SrcIsMin = IRB.CreateICmp(CmpInst::ICMP_EQ, Src, MinValVec);
4595+
4596+
Value *PoisonedShadow = getPoisonedShadow(Src);
4597+
Value *PoisonedIfIntMinShadow =
4598+
IRB.CreateSelect(SrcIsMin, PoisonedShadow, SrcShadow);
4599+
Value *Shadow =
4600+
IRB.CreateSelect(IsIntMinPoison, PoisonedIfIntMinShadow, SrcShadow);
4601+
4602+
setShadow(&I, Shadow);
45824603
setOrigin(&I, getOrigin(&I, 0));
45834604
}
45844605

‎llvm/test/Instrumentation/MemorySanitizer/X86/avx512-intrinsics-upgrade.ll‎

Lines changed: 22 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -11436,8 +11436,11 @@ define <16 x i32>@test_int_x86_avx512_pabs_d_512(<16 x i32> %x0, <16 x i32> %x1)
1143611436
; CHECK-LABEL: @test_int_x86_avx512_pabs_d_512(
1143711437
; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 8
1143811438
; CHECK-NEXT: call void @llvm.donothing()
11439-
; CHECK-NEXT: [[TMP2:%.*]] = call <16 x i32> @llvm.abs.v16i32(<16 x i32> [[X0:%.*]], i1 false)
11440-
; CHECK-NEXT: store <16 x i32> [[TMP1]], ptr @__msan_retval_tls, align 8
11439+
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq <16 x i32> [[X0:%.*]], splat (i32 -2147483648)
11440+
; CHECK-NEXT: [[TMP3:%.*]] = select <16 x i1> [[TMP5]], <16 x i32> splat (i32 -1), <16 x i32> [[TMP1]]
11441+
; CHECK-NEXT: [[TMP4:%.*]] = select i1 false, <16 x i32> [[TMP3]], <16 x i32> [[TMP1]]
11442+
; CHECK-NEXT: [[TMP2:%.*]] = call <16 x i32> @llvm.abs.v16i32(<16 x i32> [[X0]], i1 false)
11443+
; CHECK-NEXT: store <16 x i32> [[TMP4]], ptr @__msan_retval_tls, align 8
1144111444
; CHECK-NEXT: ret <16 x i32> [[TMP2]]
1144211445
;
1144311446
%res = call <16 x i32> @llvm.x86.avx512.mask.pabs.d.512(<16 x i32> %x0, <16 x i32> %x1, i16 -1)
@@ -11451,12 +11454,15 @@ define <16 x i32>@test_int_x86_avx512_mask_pabs_d_512(<16 x i32> %x0, <16 x i32>
1145111454
; CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 128) to ptr), align 8
1145211455
; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 64) to ptr), align 8
1145311456
; CHECK-NEXT: call void @llvm.donothing()
11454-
; CHECK-NEXT: [[TMP4:%.*]] = call <16 x i32> @llvm.abs.v16i32(<16 x i32> [[X0:%.*]], i1 false)
11457+
; CHECK-NEXT: [[TMP12:%.*]] = icmp eq <16 x i32> [[X0:%.*]], splat (i32 -2147483648)
11458+
; CHECK-NEXT: [[TMP13:%.*]] = select <16 x i1> [[TMP12]], <16 x i32> splat (i32 -1), <16 x i32> [[TMP1]]
11459+
; CHECK-NEXT: [[TMP14:%.*]] = select i1 false, <16 x i32> [[TMP13]], <16 x i32> [[TMP1]]
11460+
; CHECK-NEXT: [[TMP4:%.*]] = call <16 x i32> @llvm.abs.v16i32(<16 x i32> [[X0]], i1 false)
1145511461
; CHECK-NEXT: [[TMP5:%.*]] = bitcast i16 [[TMP2]] to <16 x i1>
1145611462
; CHECK-NEXT: [[TMP6:%.*]] = bitcast i16 [[X2:%.*]] to <16 x i1>
11457-
; CHECK-NEXT: [[TMP7:%.*]] = select <16 x i1> [[TMP6]], <16 x i32> [[TMP1]], <16 x i32> [[TMP3]]
11463+
; CHECK-NEXT: [[TMP7:%.*]] = select <16 x i1> [[TMP6]], <16 x i32> [[TMP14]], <16 x i32> [[TMP3]]
1145811464
; CHECK-NEXT: [[TMP8:%.*]] = xor <16 x i32> [[TMP4]], [[X1:%.*]]
11459-
; CHECK-NEXT: [[TMP9:%.*]] = or <16 x i32> [[TMP8]], [[TMP1]]
11465+
; CHECK-NEXT: [[TMP9:%.*]] = or <16 x i32> [[TMP8]], [[TMP14]]
1146011466
; CHECK-NEXT: [[TMP10:%.*]] = or <16 x i32> [[TMP9]], [[TMP3]]
1146111467
; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <16 x i1> [[TMP5]], <16 x i32> [[TMP10]], <16 x i32> [[TMP7]]
1146211468
; CHECK-NEXT: [[TMP11:%.*]] = select <16 x i1> [[TMP6]], <16 x i32> [[TMP4]], <16 x i32> [[X1]]
@@ -11473,8 +11479,11 @@ define <8 x i64>@test_int_x86_avx512_pabs_q_512(<8 x i64> %x0, <8 x i64> %x1, i8
1147311479
; CHECK-LABEL: @test_int_x86_avx512_pabs_q_512(
1147411480
; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 8
1147511481
; CHECK-NEXT: call void @llvm.donothing()
11476-
; CHECK-NEXT: [[TMP2:%.*]] = call <8 x i64> @llvm.abs.v8i64(<8 x i64> [[X0:%.*]], i1 false)
11477-
; CHECK-NEXT: store <8 x i64> [[TMP1]], ptr @__msan_retval_tls, align 8
11482+
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq <8 x i64> [[X0:%.*]], splat (i64 -9223372036854775808)
11483+
; CHECK-NEXT: [[TMP3:%.*]] = select <8 x i1> [[TMP5]], <8 x i64> splat (i64 -1), <8 x i64> [[TMP1]]
11484+
; CHECK-NEXT: [[TMP4:%.*]] = select i1 false, <8 x i64> [[TMP3]], <8 x i64> [[TMP1]]
11485+
; CHECK-NEXT: [[TMP2:%.*]] = call <8 x i64> @llvm.abs.v8i64(<8 x i64> [[X0]], i1 false)
11486+
; CHECK-NEXT: store <8 x i64> [[TMP4]], ptr @__msan_retval_tls, align 8
1147811487
; CHECK-NEXT: ret <8 x i64> [[TMP2]]
1147911488
;
1148011489
%res = call <8 x i64> @llvm.x86.avx512.mask.pabs.q.512(<8 x i64> %x0, <8 x i64> %x1, i8 -1)
@@ -11488,12 +11497,15 @@ define <8 x i64>@test_int_x86_avx512_mask_pabs_q_512(<8 x i64> %x0, <8 x i64> %x
1148811497
; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 128) to ptr), align 8
1148911498
; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 64) to ptr), align 8
1149011499
; CHECK-NEXT: call void @llvm.donothing()
11491-
; CHECK-NEXT: [[TMP4:%.*]] = call <8 x i64> @llvm.abs.v8i64(<8 x i64> [[X0:%.*]], i1 false)
11500+
; CHECK-NEXT: [[TMP12:%.*]] = icmp eq <8 x i64> [[X0:%.*]], splat (i64 -9223372036854775808)
11501+
; CHECK-NEXT: [[TMP13:%.*]] = select <8 x i1> [[TMP12]], <8 x i64> splat (i64 -1), <8 x i64> [[TMP1]]
11502+
; CHECK-NEXT: [[TMP14:%.*]] = select i1 false, <8 x i64> [[TMP13]], <8 x i64> [[TMP1]]
11503+
; CHECK-NEXT: [[TMP4:%.*]] = call <8 x i64> @llvm.abs.v8i64(<8 x i64> [[X0]], i1 false)
1149211504
; CHECK-NEXT: [[TMP5:%.*]] = bitcast i8 [[TMP2]] to <8 x i1>
1149311505
; CHECK-NEXT: [[TMP6:%.*]] = bitcast i8 [[X2:%.*]] to <8 x i1>
11494-
; CHECK-NEXT: [[TMP7:%.*]] = select <8 x i1> [[TMP6]], <8 x i64> [[TMP1]], <8 x i64> [[TMP3]]
11506+
; CHECK-NEXT: [[TMP7:%.*]] = select <8 x i1> [[TMP6]], <8 x i64> [[TMP14]], <8 x i64> [[TMP3]]
1149511507
; CHECK-NEXT: [[TMP8:%.*]] = xor <8 x i64> [[TMP4]], [[X1:%.*]]
11496-
; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i64> [[TMP8]], [[TMP1]]
11508+
; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i64> [[TMP8]], [[TMP14]]
1149711509
; CHECK-NEXT: [[TMP10:%.*]] = or <8 x i64> [[TMP9]], [[TMP3]]
1149811510
; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP5]], <8 x i64> [[TMP10]], <8 x i64> [[TMP7]]
1149911511
; CHECK-NEXT: [[TMP11:%.*]] = select <8 x i1> [[TMP6]], <8 x i64> [[TMP4]], <8 x i64> [[X1]]

‎llvm/test/Instrumentation/MemorySanitizer/X86/avx512bw-intrinsics-upgrade.ll‎

Lines changed: 22 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -4443,8 +4443,11 @@ define <32 x i16> @test_int_x86_avx512_pabs_w_512(<32 x i16> %x0, <32 x i16> %x1
44434443
; CHECK-LABEL: @test_int_x86_avx512_pabs_w_512(
44444444
; CHECK-NEXT: [[TMP1:%.*]] = load <32 x i16>, ptr @__msan_param_tls, align 8
44454445
; CHECK-NEXT: call void @llvm.donothing()
4446-
; CHECK-NEXT: [[TMP2:%.*]] = call <32 x i16> @llvm.abs.v32i16(<32 x i16> [[X0:%.*]], i1 false)
4447-
; CHECK-NEXT: store <32 x i16> [[TMP1]], ptr @__msan_retval_tls, align 8
4446+
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq <32 x i16> [[X0:%.*]], splat (i16 -32768)
4447+
; CHECK-NEXT: [[TMP3:%.*]] = select <32 x i1> [[TMP5]], <32 x i16> splat (i16 -1), <32 x i16> [[TMP1]]
4448+
; CHECK-NEXT: [[TMP4:%.*]] = select i1 false, <32 x i16> [[TMP3]], <32 x i16> [[TMP1]]
4449+
; CHECK-NEXT: [[TMP2:%.*]] = call <32 x i16> @llvm.abs.v32i16(<32 x i16> [[X0]], i1 false)
4450+
; CHECK-NEXT: store <32 x i16> [[TMP4]], ptr @__msan_retval_tls, align 8
44484451
; CHECK-NEXT: ret <32 x i16> [[TMP2]]
44494452
;
44504453
%res = call <32 x i16> @llvm.x86.avx512.mask.pabs.w.512(<32 x i16> %x0, <32 x i16> %x1, i32 -1)
@@ -4457,12 +4460,15 @@ define <32 x i16> @test_int_x86_avx512_mask_pabs_w_512(<32 x i16> %x0, <32 x i16
44574460
; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 128) to ptr), align 8
44584461
; CHECK-NEXT: [[TMP3:%.*]] = load <32 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 64) to ptr), align 8
44594462
; CHECK-NEXT: call void @llvm.donothing()
4460-
; CHECK-NEXT: [[TMP4:%.*]] = call <32 x i16> @llvm.abs.v32i16(<32 x i16> [[X0:%.*]], i1 false)
4463+
; CHECK-NEXT: [[TMP12:%.*]] = icmp eq <32 x i16> [[X0:%.*]], splat (i16 -32768)
4464+
; CHECK-NEXT: [[TMP13:%.*]] = select <32 x i1> [[TMP12]], <32 x i16> splat (i16 -1), <32 x i16> [[TMP1]]
4465+
; CHECK-NEXT: [[TMP14:%.*]] = select i1 false, <32 x i16> [[TMP13]], <32 x i16> [[TMP1]]
4466+
; CHECK-NEXT: [[TMP4:%.*]] = call <32 x i16> @llvm.abs.v32i16(<32 x i16> [[X0]], i1 false)
44614467
; CHECK-NEXT: [[TMP5:%.*]] = bitcast i32 [[TMP2]] to <32 x i1>
44624468
; CHECK-NEXT: [[TMP6:%.*]] = bitcast i32 [[X2:%.*]] to <32 x i1>
4463-
; CHECK-NEXT: [[TMP7:%.*]] = select <32 x i1> [[TMP6]], <32 x i16> [[TMP1]], <32 x i16> [[TMP3]]
4469+
; CHECK-NEXT: [[TMP7:%.*]] = select <32 x i1> [[TMP6]], <32 x i16> [[TMP14]], <32 x i16> [[TMP3]]
44644470
; CHECK-NEXT: [[TMP8:%.*]] = xor <32 x i16> [[TMP4]], [[X1:%.*]]
4465-
; CHECK-NEXT: [[TMP9:%.*]] = or <32 x i16> [[TMP8]], [[TMP1]]
4471+
; CHECK-NEXT: [[TMP9:%.*]] = or <32 x i16> [[TMP8]], [[TMP14]]
44664472
; CHECK-NEXT: [[TMP10:%.*]] = or <32 x i16> [[TMP9]], [[TMP3]]
44674473
; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <32 x i1> [[TMP5]], <32 x i16> [[TMP10]], <32 x i16> [[TMP7]]
44684474
; CHECK-NEXT: [[TMP11:%.*]] = select <32 x i1> [[TMP6]], <32 x i16> [[TMP4]], <32 x i16> [[X1]]
@@ -4479,8 +4485,11 @@ define <64 x i8> @test_int_x86_avx512_pabs_b_512(<64 x i8> %x0, <64 x i8> %x1) n
44794485
; CHECK-LABEL: @test_int_x86_avx512_pabs_b_512(
44804486
; CHECK-NEXT: [[TMP1:%.*]] = load <64 x i8>, ptr @__msan_param_tls, align 8
44814487
; CHECK-NEXT: call void @llvm.donothing()
4482-
; CHECK-NEXT: [[TMP2:%.*]] = call <64 x i8> @llvm.abs.v64i8(<64 x i8> [[X0:%.*]], i1 false)
4483-
; CHECK-NEXT: store <64 x i8> [[TMP1]], ptr @__msan_retval_tls, align 8
4488+
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq <64 x i8> [[X0:%.*]], splat (i8 -128)
4489+
; CHECK-NEXT: [[TMP3:%.*]] = select <64 x i1> [[TMP5]], <64 x i8> splat (i8 -1), <64 x i8> [[TMP1]]
4490+
; CHECK-NEXT: [[TMP4:%.*]] = select i1 false, <64 x i8> [[TMP3]], <64 x i8> [[TMP1]]
4491+
; CHECK-NEXT: [[TMP2:%.*]] = call <64 x i8> @llvm.abs.v64i8(<64 x i8> [[X0]], i1 false)
4492+
; CHECK-NEXT: store <64 x i8> [[TMP4]], ptr @__msan_retval_tls, align 8
44844493
; CHECK-NEXT: ret <64 x i8> [[TMP2]]
44854494
;
44864495
%res = call <64 x i8> @llvm.x86.avx512.mask.pabs.b.512(<64 x i8> %x0, <64 x i8> %x1, i64 -1)
@@ -4493,12 +4502,15 @@ define <64 x i8> @test_int_x86_avx512_mask_pabs_b_512(<64 x i8> %x0, <64 x i8> %
44934502
; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 128) to ptr), align 8
44944503
; CHECK-NEXT: [[TMP3:%.*]] = load <64 x i8>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 64) to ptr), align 8
44954504
; CHECK-NEXT: call void @llvm.donothing()
4496-
; CHECK-NEXT: [[TMP4:%.*]] = call <64 x i8> @llvm.abs.v64i8(<64 x i8> [[X0:%.*]], i1 false)
4505+
; CHECK-NEXT: [[TMP12:%.*]] = icmp eq <64 x i8> [[X0:%.*]], splat (i8 -128)
4506+
; CHECK-NEXT: [[TMP13:%.*]] = select <64 x i1> [[TMP12]], <64 x i8> splat (i8 -1), <64 x i8> [[TMP1]]
4507+
; CHECK-NEXT: [[TMP14:%.*]] = select i1 false, <64 x i8> [[TMP13]], <64 x i8> [[TMP1]]
4508+
; CHECK-NEXT: [[TMP4:%.*]] = call <64 x i8> @llvm.abs.v64i8(<64 x i8> [[X0]], i1 false)
44974509
; CHECK-NEXT: [[TMP5:%.*]] = bitcast i64 [[TMP2]] to <64 x i1>
44984510
; CHECK-NEXT: [[TMP6:%.*]] = bitcast i64 [[X2:%.*]] to <64 x i1>
4499-
; CHECK-NEXT: [[TMP7:%.*]] = select <64 x i1> [[TMP6]], <64 x i8> [[TMP1]], <64 x i8> [[TMP3]]
4511+
; CHECK-NEXT: [[TMP7:%.*]] = select <64 x i1> [[TMP6]], <64 x i8> [[TMP14]], <64 x i8> [[TMP3]]
45004512
; CHECK-NEXT: [[TMP8:%.*]] = xor <64 x i8> [[TMP4]], [[X1:%.*]]
4501-
; CHECK-NEXT: [[TMP9:%.*]] = or <64 x i8> [[TMP8]], [[TMP1]]
4513+
; CHECK-NEXT: [[TMP9:%.*]] = or <64 x i8> [[TMP8]], [[TMP14]]
45024514
; CHECK-NEXT: [[TMP10:%.*]] = or <64 x i8> [[TMP9]], [[TMP3]]
45034515
; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <64 x i1> [[TMP5]], <64 x i8> [[TMP10]], <64 x i8> [[TMP7]]
45044516
; CHECK-NEXT: [[TMP11:%.*]] = select <64 x i1> [[TMP6]], <64 x i8> [[TMP4]], <64 x i8> [[X1]]

‎llvm/test/Instrumentation/MemorySanitizer/abs-vector.ll‎

Lines changed: 48 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -6,19 +6,22 @@ target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16
66
target triple = "x86_64-unknown-linux-gnu"
77

88
define <4 x i64> @test_mm256_abs_epi8(<4 x i64> %a) local_unnamed_addr #0 {
9-
; CHECK-LABEL: @test_mm256_abs_epi8(
10-
; CHECK-NEXT: entry:
11-
; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8
12-
; ORIGIN-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4
13-
; CHECK: call void @llvm.donothing()
14-
; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i64> [[TMP0]] to <32 x i8>
15-
; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i64> [[A:%.*]] to <32 x i8>
16-
; CHECK-NEXT: [[TMP4:%.*]] = tail call <32 x i8> @llvm.abs.v32i8(<32 x i8> [[TMP3]], i1 false)
17-
; CHECK-NEXT: [[TMP5:%.*]] = bitcast <32 x i8> [[TMP2]] to <4 x i64>
18-
; CHECK-NEXT: [[TMP6:%.*]] = bitcast <32 x i8> [[TMP4]] to <4 x i64>
19-
; CHECK-NEXT: store <4 x i64> [[TMP5]], ptr @__msan_retval_tls, align 8
20-
; ORIGIN-NEXT: store i32 [[TMP1]], ptr @__msan_retval_origin_tls, align 4
21-
; CHECK: ret <4 x i64> [[TMP6]]
9+
; ORIGIN-LABEL: @test_mm256_abs_epi8(
10+
; ORIGIN-NEXT: entry:
11+
; ORIGIN-NEXT: [[TMP0:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8
12+
; ORIGIN-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4
13+
; ORIGIN-NEXT: call void @llvm.donothing()
14+
; ORIGIN-NEXT: [[TMP2:%.*]] = bitcast <4 x i64> [[TMP0]] to <32 x i8>
15+
; ORIGIN-NEXT: [[TMP3:%.*]] = bitcast <4 x i64> [[A:%.*]] to <32 x i8>
16+
; ORIGIN-NEXT: [[TMP4:%.*]] = icmp eq <32 x i8> [[TMP3]], splat (i8 -128)
17+
; ORIGIN-NEXT: [[TMP5:%.*]] = select <32 x i1> [[TMP4]], <32 x i8> splat (i8 -1), <32 x i8> [[TMP2]]
18+
; ORIGIN-NEXT: [[TMP6:%.*]] = select i1 false, <32 x i8> [[TMP5]], <32 x i8> [[TMP2]]
19+
; ORIGIN-NEXT: [[TMP7:%.*]] = tail call <32 x i8> @llvm.abs.v32i8(<32 x i8> [[TMP3]], i1 false)
20+
; ORIGIN-NEXT: [[TMP8:%.*]] = bitcast <32 x i8> [[TMP6]] to <4 x i64>
21+
; ORIGIN-NEXT: [[TMP9:%.*]] = bitcast <32 x i8> [[TMP7]] to <4 x i64>
22+
; ORIGIN-NEXT: store <4 x i64> [[TMP8]], ptr @__msan_retval_tls, align 8
23+
; ORIGIN-NEXT: store i32 [[TMP1]], ptr @__msan_retval_origin_tls, align 4
24+
; ORIGIN-NEXT: ret <4 x i64> [[TMP9]]
2225
;
2326
entry:
2427
%0 = bitcast <4 x i64> %a to <32 x i8>
@@ -28,19 +31,22 @@ entry:
2831
}
2932

3033
define <4 x i64> @test_mm256_abs_epi16(<4 x i64> %a) local_unnamed_addr #0 {
31-
; CHECK-LABEL: @test_mm256_abs_epi16(
32-
; CHECK-NEXT: entry:
33-
; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8
34-
; ORIGIN-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4
35-
; CHECK: call void @llvm.donothing()
36-
; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i64> [[TMP0]] to <16 x i16>
37-
; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i64> [[A:%.*]] to <16 x i16>
38-
; CHECK-NEXT: [[TMP4:%.*]] = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> [[TMP3]], i1 false)
39-
; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i16> [[TMP2]] to <4 x i64>
40-
; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i16> [[TMP4]] to <4 x i64>
41-
; CHECK-NEXT: store <4 x i64> [[TMP5]], ptr @__msan_retval_tls, align 8
42-
; ORIGIN-NEXT: store i32 [[TMP1]], ptr @__msan_retval_origin_tls, align 4
43-
; CHECK: ret <4 x i64> [[TMP6]]
34+
; ORIGIN-LABEL: @test_mm256_abs_epi16(
35+
; ORIGIN-NEXT: entry:
36+
; ORIGIN-NEXT: [[TMP0:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8
37+
; ORIGIN-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4
38+
; ORIGIN-NEXT: call void @llvm.donothing()
39+
; ORIGIN-NEXT: [[TMP2:%.*]] = bitcast <4 x i64> [[TMP0]] to <16 x i16>
40+
; ORIGIN-NEXT: [[TMP3:%.*]] = bitcast <4 x i64> [[A:%.*]] to <16 x i16>
41+
; ORIGIN-NEXT: [[TMP4:%.*]] = icmp eq <16 x i16> [[TMP3]], splat (i16 -32768)
42+
; ORIGIN-NEXT: [[TMP5:%.*]] = select <16 x i1> [[TMP4]], <16 x i16> splat (i16 -1), <16 x i16> [[TMP2]]
43+
; ORIGIN-NEXT: [[TMP6:%.*]] = select i1 false, <16 x i16> [[TMP5]], <16 x i16> [[TMP2]]
44+
; ORIGIN-NEXT: [[TMP7:%.*]] = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> [[TMP3]], i1 false)
45+
; ORIGIN-NEXT: [[TMP8:%.*]] = bitcast <16 x i16> [[TMP6]] to <4 x i64>
46+
; ORIGIN-NEXT: [[TMP9:%.*]] = bitcast <16 x i16> [[TMP7]] to <4 x i64>
47+
; ORIGIN-NEXT: store <4 x i64> [[TMP8]], ptr @__msan_retval_tls, align 8
48+
; ORIGIN-NEXT: store i32 [[TMP1]], ptr @__msan_retval_origin_tls, align 4
49+
; ORIGIN-NEXT: ret <4 x i64> [[TMP9]]
4450
;
4551
entry:
4652
%0 = bitcast <4 x i64> %a to <16 x i16>
@@ -50,19 +56,22 @@ entry:
5056
}
5157

5258
define <4 x i64> @test_mm256_abs_epi32(<4 x i64> %a) local_unnamed_addr #0 {
53-
; CHECK-LABEL: @test_mm256_abs_epi32(
54-
; CHECK-NEXT: entry:
55-
; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8
56-
; ORIGIN-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4
57-
; CHECK: call void @llvm.donothing()
58-
; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i64> [[TMP0]] to <8 x i32>
59-
; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i64> [[A:%.*]] to <8 x i32>
60-
; CHECK-NEXT: [[TMP4:%.*]] = tail call <8 x i32> @llvm.abs.v8i32(<8 x i32> [[TMP3]], i1 false)
61-
; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i32> [[TMP2]] to <4 x i64>
62-
; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i32> [[TMP4]] to <4 x i64>
63-
; CHECK-NEXT: store <4 x i64> [[TMP5]], ptr @__msan_retval_tls, align 8
64-
; ORIGIN-NEXT: store i32 [[TMP1]], ptr @__msan_retval_origin_tls, align 4
65-
; CHECK: ret <4 x i64> [[TMP6]]
59+
; ORIGIN-LABEL: @test_mm256_abs_epi32(
60+
; ORIGIN-NEXT: entry:
61+
; ORIGIN-NEXT: [[TMP0:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8
62+
; ORIGIN-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4
63+
; ORIGIN-NEXT: call void @llvm.donothing()
64+
; ORIGIN-NEXT: [[TMP2:%.*]] = bitcast <4 x i64> [[TMP0]] to <8 x i32>
65+
; ORIGIN-NEXT: [[TMP3:%.*]] = bitcast <4 x i64> [[A:%.*]] to <8 x i32>
66+
; ORIGIN-NEXT: [[TMP4:%.*]] = icmp eq <8 x i32> [[TMP3]], splat (i32 -2147483648)
67+
; ORIGIN-NEXT: [[TMP5:%.*]] = select <8 x i1> [[TMP4]], <8 x i32> splat (i32 -1), <8 x i32> [[TMP2]]
68+
; ORIGIN-NEXT: [[TMP6:%.*]] = select i1 false, <8 x i32> [[TMP5]], <8 x i32> [[TMP2]]
69+
; ORIGIN-NEXT: [[TMP7:%.*]] = tail call <8 x i32> @llvm.abs.v8i32(<8 x i32> [[TMP3]], i1 false)
70+
; ORIGIN-NEXT: [[TMP8:%.*]] = bitcast <8 x i32> [[TMP6]] to <4 x i64>
71+
; ORIGIN-NEXT: [[TMP9:%.*]] = bitcast <8 x i32> [[TMP7]] to <4 x i64>
72+
; ORIGIN-NEXT: store <4 x i64> [[TMP8]], ptr @__msan_retval_tls, align 8
73+
; ORIGIN-NEXT: store i32 [[TMP1]], ptr @__msan_retval_origin_tls, align 4
74+
; ORIGIN-NEXT: ret <4 x i64> [[TMP9]]
6675
;
6776
entry:
6877
%0 = bitcast <4 x i64> %a to <8 x i32>

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