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[CostModel/RISCV] Fix costs of [l]lrint, [l]lround
1 parent b200011 commit 6fc7e25

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5 files changed

+2047
-70
lines changed

5 files changed

+2047
-70
lines changed

llvm/include/llvm/CodeGen/BasicTTIImpl.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2290,6 +2290,12 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {
22902290
case Intrinsic::llrint:
22912291
ISD = ISD::LLRINT;
22922292
break;
2293+
case Intrinsic::lround:
2294+
ISD = ISD::LROUND;
2295+
break;
2296+
case Intrinsic::llround:
2297+
ISD = ISD::LLROUND;
2298+
break;
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case Intrinsic::round:
22942300
ISD = ISD::FROUND;
22952301
break;

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

Lines changed: 23 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1191,9 +1191,6 @@ static const CostTblEntry VectorIntrinsicCostTable[]{
11911191
{Intrinsic::roundeven, MVT::f64, 9},
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{Intrinsic::rint, MVT::f32, 7},
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{Intrinsic::rint, MVT::f64, 7},
1194-
{Intrinsic::lrint, MVT::i32, 1},
1195-
{Intrinsic::lrint, MVT::i64, 1},
1196-
{Intrinsic::llrint, MVT::i64, 1},
11971194
{Intrinsic::nearbyint, MVT::f32, 9},
11981195
{Intrinsic::nearbyint, MVT::f64, 9},
11991196
{Intrinsic::bswap, MVT::i16, 3},
@@ -1262,11 +1259,29 @@ RISCVTTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
12621259
switch (ICA.getID()) {
12631260
case Intrinsic::lrint:
12641261
case Intrinsic::llrint:
1265-
// We can't currently lower half or bfloat vector lrint/llrint.
1266-
if (auto *VecTy = dyn_cast<VectorType>(ICA.getArgTypes()[0]);
1267-
VecTy && VecTy->getElementType()->is16bitFPTy())
1268-
return InstructionCost::getInvalid();
1269-
[[fallthrough]];
1262+
case Intrinsic::lround:
1263+
case Intrinsic::llround: {
1264+
auto LT = getTypeLegalizationCost(RetTy);
1265+
switch (ICA.getID()) {
1266+
case Intrinsic::lrint:
1267+
case Intrinsic::llrint:
1268+
// We can't currently lower half or bfloat vector lrint/llrint.
1269+
if (auto *VecTy = dyn_cast<VectorType>(ICA.getArgTypes()[0]);
1270+
VecTy && VecTy->getElementType()->is16bitFPTy())
1271+
return InstructionCost::getInvalid();
1272+
break;
1273+
case Intrinsic::lround:
1274+
case Intrinsic::llround:
1275+
// We can't currently lower scalable-vector lround/llround.
1276+
if (LT.second.isScalableVector())
1277+
return InstructionCost::getInvalid();
1278+
break;
1279+
}
1280+
if (ST->hasVInstructions() && LT.second.isVector())
1281+
return LT.first *
1282+
getRISCVInstructionCost(RISCV::VFCVT_X_F_V, LT.second, CostKind);
1283+
break;
1284+
}
12701285
case Intrinsic::ceil:
12711286
case Intrinsic::floor:
12721287
case Intrinsic::trunc:

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