@@ -1423,7 +1423,7 @@ Register RAGreedy::tryInstructionSplit(const LiveInterval &VirtReg,
14231423 bool SplitSubClass = true ;
14241424 if (!RegClassInfo.isProperSubClass (CurRC)) {
14251425 if (!VirtReg.hasSubRanges ())
1426- return 0 ;
1426+ return Register () ;
14271427 SplitSubClass = false ;
14281428 }
14291429
@@ -1434,7 +1434,7 @@ Register RAGreedy::tryInstructionSplit(const LiveInterval &VirtReg,
14341434
14351435 ArrayRef<SlotIndex> Uses = SA->getUseSlots ();
14361436 if (Uses.size () <= 1 )
1437- return 0 ;
1437+ return Register () ;
14381438
14391439 LLVM_DEBUG (dbgs () << " Split around " << Uses.size ()
14401440 << " individual instrs.\n " );
@@ -1586,7 +1586,7 @@ Register RAGreedy::tryLocalSplit(const LiveInterval &VirtReg,
15861586
15871587 ArrayRef<SlotIndex> Uses = SA->getUseSlots ();
15881588 if (Uses.size () <= 2 )
1589- return 0 ;
1589+ return Register () ;
15901590 const unsigned NumGaps = Uses.size ()-1 ;
15911591
15921592 LLVM_DEBUG ({
@@ -2184,7 +2184,7 @@ MCRegister RAGreedy::selectOrSplit(const LiveInterval &VirtReg,
21842184// / range can have lower cost than using the CSR for the first time;
21852185// / Spilling a live range in the cold path can have lower cost than using
21862186// / the CSR for the first time. Returns the physical register if we decide
2187- // / to use the CSR; otherwise return 0 .
2187+ // / to use the CSR; otherwise return MCRegister() .
21882188MCRegister RAGreedy::tryAssignCSRFirstTime (
21892189 const LiveInterval &VirtReg, AllocationOrder &Order, MCRegister PhysReg,
21902190 uint8_t &CostPerUseLimit, SmallVectorImpl<Register> &NewVRegs) {
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