@@ -36,13 +36,9 @@ define i32 @add_select_cmp_and2(i32 %in) {
3636
3737define i32 @add_select_cmp_and3 (i32 %in ) {
3838; CHECK-LABEL: @add_select_cmp_and3(
39- ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[IN:%.*]], 3
40- ; CHECK-NEXT: [[TEMP:%.*]] = mul nuw nsw i32 [[TMP1]], 72
41- ; CHECK-NEXT: [[BITOP2:%.*]] = and i32 [[IN]], 4
42- ; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[BITOP2]], 0
43- ; CHECK-NEXT: [[SEL2:%.*]] = select i1 [[CMP2]], i32 0, i32 288
44- ; CHECK-NEXT: [[OUT:%.*]] = or disjoint i32 [[TEMP]], [[SEL2]]
45- ; CHECK-NEXT: ret i32 [[OUT]]
39+ ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[IN:%.*]], 7
40+ ; CHECK-NEXT: [[TEMP1:%.*]] = mul nuw nsw i32 [[TMP1]], 72
41+ ; CHECK-NEXT: ret i32 [[TEMP1]]
4642;
4743 %bitop0 = and i32 %in , 1
4844 %cmp0 = icmp eq i32 %bitop0 , 0
@@ -60,12 +56,9 @@ define i32 @add_select_cmp_and3(i32 %in) {
6056
6157define i32 @add_select_cmp_and4 (i32 %in ) {
6258; CHECK-LABEL: @add_select_cmp_and4(
63- ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[IN:%.*]], 3
64- ; CHECK-NEXT: [[OUT:%.*]] = mul nuw nsw i32 [[TMP1]], 72
65- ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[IN]], 12
66- ; CHECK-NEXT: [[TEMP3:%.*]] = mul nuw nsw i32 [[TMP2]], 72
67- ; CHECK-NEXT: [[OUT1:%.*]] = or disjoint i32 [[OUT]], [[TEMP3]]
68- ; CHECK-NEXT: ret i32 [[OUT1]]
59+ ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[IN:%.*]], 15
60+ ; CHECK-NEXT: [[TEMP2:%.*]] = mul nuw nsw i32 [[TMP2]], 72
61+ ; CHECK-NEXT: ret i32 [[TEMP2]]
6962;
7063 %bitop0 = and i32 %in , 1
7164 %cmp0 = icmp eq i32 %bitop0 , 0
@@ -361,6 +354,103 @@ define i64 @mask_select_types_1(i64 %in) {
361354 ret i64 %out
362355}
363356
357+ define i32 @add_select_cmp_mixed1 (i32 %in ) {
358+ ; CHECK-LABEL: @add_select_cmp_mixed1(
359+ ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[IN:%.*]], 3
360+ ; CHECK-NEXT: [[OUT:%.*]] = mul nuw nsw i32 [[TMP1]], 72
361+ ; CHECK-NEXT: ret i32 [[OUT]]
362+ ;
363+ %mask = and i32 %in , 1
364+ %sel0 = mul i32 %mask , 72
365+ %bitop1 = and i32 %in , 2
366+ %cmp1 = icmp eq i32 %bitop1 , 0
367+ %sel1 = select i1 %cmp1 , i32 0 , i32 144
368+ %out = or disjoint i32 %sel0 , %sel1
369+ ret i32 %out
370+ }
371+
372+ define i32 @add_select_cmp_mixed2 (i32 %in ) {
373+ ; CHECK-LABEL: @add_select_cmp_mixed2(
374+ ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[IN:%.*]], 3
375+ ; CHECK-NEXT: [[OUT:%.*]] = mul nuw nsw i32 [[TMP1]], 72
376+ ; CHECK-NEXT: ret i32 [[OUT]]
377+ ;
378+ %bitop0 = and i32 %in , 1
379+ %cmp0 = icmp eq i32 %bitop0 , 0
380+ %mask = and i32 %in , 2
381+ %sel0 = select i1 %cmp0 , i32 0 , i32 72
382+ %sel1 = mul i32 %mask , 72
383+ %out = or disjoint i32 %sel0 , %sel1
384+ ret i32 %out
385+ }
386+
387+ define i32 @add_select_cmp_and_mul (i32 %in ) {
388+ ; CHECK-LABEL: @add_select_cmp_and_mul(
389+ ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[IN:%.*]], 3
390+ ; CHECK-NEXT: [[OUT:%.*]] = mul nuw nsw i32 [[TMP1]], 72
391+ ; CHECK-NEXT: ret i32 [[OUT]]
392+ ;
393+ %mask0 = and i32 %in , 1
394+ %sel0 = mul i32 %mask0 , 72
395+ %mask1 = and i32 %in , 2
396+ %sel1 = mul i32 %mask1 , 72
397+ %out = or disjoint i32 %sel0 , %sel1
398+ ret i32 %out
399+ }
400+
401+ define i32 @add_select_cmp_mixed2_mismatch (i32 %in ) {
402+ ; CHECK-LABEL: @add_select_cmp_mixed2_mismatch(
403+ ; CHECK-NEXT: [[BITOP0:%.*]] = and i32 [[IN:%.*]], 1
404+ ; CHECK-NEXT: [[CMP0:%.*]] = icmp eq i32 [[BITOP0]], 0
405+ ; CHECK-NEXT: [[MASK:%.*]] = and i32 [[IN]], 2
406+ ; CHECK-NEXT: [[SEL0:%.*]] = select i1 [[CMP0]], i32 0, i32 73
407+ ; CHECK-NEXT: [[SEL1:%.*]] = mul nuw nsw i32 [[MASK]], 72
408+ ; CHECK-NEXT: [[OUT:%.*]] = or disjoint i32 [[SEL0]], [[SEL1]]
409+ ; CHECK-NEXT: ret i32 [[OUT]]
410+ ;
411+ %bitop0 = and i32 %in , 1
412+ %cmp0 = icmp eq i32 %bitop0 , 0
413+ %mask = and i32 %in , 2
414+ %sel0 = select i1 %cmp0 , i32 0 , i32 73
415+ %sel1 = mul i32 %mask , 72
416+ %out = or disjoint i32 %sel0 , %sel1
417+ ret i32 %out
418+ }
419+
420+ define i32 @add_select_cmp_and_mul_mismatch (i32 %in ) {
421+ ; CHECK-LABEL: @add_select_cmp_and_mul_mismatch(
422+ ; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[IN:%.*]] to i1
423+ ; CHECK-NEXT: [[SEL0:%.*]] = select i1 [[TMP1]], i32 73, i32 0
424+ ; CHECK-NEXT: [[MASK1:%.*]] = and i32 [[IN]], 2
425+ ; CHECK-NEXT: [[SEL1:%.*]] = mul nuw nsw i32 [[MASK1]], 72
426+ ; CHECK-NEXT: [[OUT:%.*]] = or disjoint i32 [[SEL0]], [[SEL1]]
427+ ; CHECK-NEXT: ret i32 [[OUT]]
428+ ;
429+ %mask0 = and i32 %in , 1
430+ %sel0 = mul i32 %mask0 , 73
431+ %mask1 = and i32 %in , 2
432+ %sel1 = mul i32 %mask1 , 72
433+ %out = or disjoint i32 %sel0 , %sel1
434+ ret i32 %out
435+ }
436+
437+ define i32 @and_mul_non_disjoint (i32 %in ) {
438+ ; CHECK-LABEL: @and_mul_non_disjoint(
439+ ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[IN:%.*]], 2
440+ ; CHECK-NEXT: [[OUT:%.*]] = mul nuw nsw i32 [[TMP1]], 72
441+ ; CHECK-NEXT: [[MASK1:%.*]] = and i32 [[IN]], 4
442+ ; CHECK-NEXT: [[SEL1:%.*]] = mul nuw nsw i32 [[MASK1]], 72
443+ ; CHECK-NEXT: [[OUT1:%.*]] = or i32 [[OUT]], [[SEL1]]
444+ ; CHECK-NEXT: ret i32 [[OUT1]]
445+ ;
446+ %mask0 = and i32 %in , 2
447+ %sel0 = mul i32 %mask0 , 72
448+ %mask1 = and i32 %in , 4
449+ %sel1 = mul i32 %mask1 , 72
450+ %out = or i32 %sel0 , %sel1
451+ ret i32 %out
452+ }
453+
364454;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
365455; CONSTSPLAT: {{.*}}
366456; CONSTVEC: {{.*}}
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