Skip to content

Commit 70368ea

Browse files
4vtomat4vtomat
authored
[RISCV] Support VLS for VCIX (#67289)
1 parent 8624075 commit 70368ea

File tree

5 files changed

+9845
-0
lines changed

5 files changed

+9845
-0
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp‎

Lines changed: 153 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8125,6 +8125,43 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
81258125
report_fatal_error("EGW should be greater than or equal to 4 * SEW.");
81268126
return Op;
81278127
}
8128+
case Intrinsic::riscv_sf_vc_v_x:
8129+
case Intrinsic::riscv_sf_vc_v_i:
8130+
case Intrinsic::riscv_sf_vc_v_xv:
8131+
case Intrinsic::riscv_sf_vc_v_iv:
8132+
case Intrinsic::riscv_sf_vc_v_vv:
8133+
case Intrinsic::riscv_sf_vc_v_fv:
8134+
case Intrinsic::riscv_sf_vc_v_xvv:
8135+
case Intrinsic::riscv_sf_vc_v_ivv:
8136+
case Intrinsic::riscv_sf_vc_v_vvv:
8137+
case Intrinsic::riscv_sf_vc_v_fvv:
8138+
case Intrinsic::riscv_sf_vc_v_xvw:
8139+
case Intrinsic::riscv_sf_vc_v_ivw:
8140+
case Intrinsic::riscv_sf_vc_v_vvw:
8141+
case Intrinsic::riscv_sf_vc_v_fvw: {
8142+
MVT VT = Op.getSimpleValueType();
8143+
8144+
if (!VT.isFixedLengthVector())
8145+
break;
8146+
8147+
SmallVector<SDValue, 6> Ops;
8148+
for (const SDValue &V : Op->op_values()) {
8149+
// Skip non-fixed vector operands.
8150+
if (!V.getValueType().isFixedLengthVector()) {
8151+
Ops.push_back(V);
8152+
continue;
8153+
}
8154+
8155+
MVT OpContainerVT =
8156+
getContainerForFixedLengthVector(V.getSimpleValueType());
8157+
Ops.push_back(convertToScalableVector(OpContainerVT, V, DAG, Subtarget));
8158+
}
8159+
8160+
MVT RetContainerVT = getContainerForFixedLengthVector(VT);
8161+
SDValue Scalable =
8162+
DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, RetContainerVT, Ops);
8163+
return convertFromScalableVector(VT, Scalable, DAG, Subtarget);
8164+
}
81288165
}
81298166

81308167
return lowerVectorIntrinsicScalars(Op, DAG, Subtarget);
@@ -8245,6 +8282,46 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
82458282
Results.push_back(Result.getValue(NF));
82468283
return DAG.getMergeValues(Results, DL);
82478284
}
8285+
case Intrinsic::riscv_sf_vc_v_x_se:
8286+
case Intrinsic::riscv_sf_vc_v_i_se:
8287+
case Intrinsic::riscv_sf_vc_v_xv_se:
8288+
case Intrinsic::riscv_sf_vc_v_iv_se:
8289+
case Intrinsic::riscv_sf_vc_v_vv_se:
8290+
case Intrinsic::riscv_sf_vc_v_fv_se:
8291+
case Intrinsic::riscv_sf_vc_v_xvv_se:
8292+
case Intrinsic::riscv_sf_vc_v_ivv_se:
8293+
case Intrinsic::riscv_sf_vc_v_vvv_se:
8294+
case Intrinsic::riscv_sf_vc_v_fvv_se:
8295+
case Intrinsic::riscv_sf_vc_v_xvw_se:
8296+
case Intrinsic::riscv_sf_vc_v_ivw_se:
8297+
case Intrinsic::riscv_sf_vc_v_vvw_se:
8298+
case Intrinsic::riscv_sf_vc_v_fvw_se: {
8299+
MVT VT = Op.getSimpleValueType();
8300+
8301+
if (!VT.isFixedLengthVector())
8302+
break;
8303+
8304+
SmallVector<SDValue, 6> Ops;
8305+
for (const SDValue &V : Op->op_values()) {
8306+
// Skip non-fixed vector operands.
8307+
if (!V.getValueType().isFixedLengthVector()) {
8308+
Ops.push_back(V);
8309+
continue;
8310+
}
8311+
8312+
MVT OpContainerVT =
8313+
getContainerForFixedLengthVector(V.getSimpleValueType());
8314+
Ops.push_back(convertToScalableVector(OpContainerVT, V, DAG, Subtarget));
8315+
}
8316+
8317+
SDLoc DL(Op);
8318+
MVT RetContainerVT = getContainerForFixedLengthVector(VT);
8319+
SDVTList VTs = DAG.getVTList({RetContainerVT, MVT::Other});
8320+
SDValue ScalableVector = DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL, VTs, Ops);
8321+
SDValue FixedVector =
8322+
convertFromScalableVector(VT, ScalableVector, DAG, Subtarget);
8323+
return DAG.getMergeValues({FixedVector, ScalableVector.getValue(1)}, DL);
8324+
}
82488325
}
82498326

82508327
return lowerVectorIntrinsicScalars(Op, DAG, Subtarget);
@@ -8332,6 +8409,82 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_VOID(SDValue Op,
83328409
ISD::INTRINSIC_VOID, DL, DAG.getVTList(MVT::Other), Ops,
83338410
FixedIntrinsic->getMemoryVT(), FixedIntrinsic->getMemOperand());
83348411
}
8412+
case Intrinsic::riscv_sf_vc_x_se_e8mf8:
8413+
case Intrinsic::riscv_sf_vc_x_se_e8mf4:
8414+
case Intrinsic::riscv_sf_vc_x_se_e8mf2:
8415+
case Intrinsic::riscv_sf_vc_x_se_e8m1:
8416+
case Intrinsic::riscv_sf_vc_x_se_e8m2:
8417+
case Intrinsic::riscv_sf_vc_x_se_e8m4:
8418+
case Intrinsic::riscv_sf_vc_x_se_e8m8:
8419+
case Intrinsic::riscv_sf_vc_x_se_e16mf4:
8420+
case Intrinsic::riscv_sf_vc_x_se_e16mf2:
8421+
case Intrinsic::riscv_sf_vc_x_se_e16m1:
8422+
case Intrinsic::riscv_sf_vc_x_se_e16m2:
8423+
case Intrinsic::riscv_sf_vc_x_se_e16m4:
8424+
case Intrinsic::riscv_sf_vc_x_se_e16m8:
8425+
case Intrinsic::riscv_sf_vc_x_se_e32mf2:
8426+
case Intrinsic::riscv_sf_vc_x_se_e32m1:
8427+
case Intrinsic::riscv_sf_vc_x_se_e32m2:
8428+
case Intrinsic::riscv_sf_vc_x_se_e32m4:
8429+
case Intrinsic::riscv_sf_vc_x_se_e32m8:
8430+
case Intrinsic::riscv_sf_vc_x_se_e64m1:
8431+
case Intrinsic::riscv_sf_vc_x_se_e64m2:
8432+
case Intrinsic::riscv_sf_vc_x_se_e64m4:
8433+
case Intrinsic::riscv_sf_vc_x_se_e64m8:
8434+
case Intrinsic::riscv_sf_vc_i_se_e8mf8:
8435+
case Intrinsic::riscv_sf_vc_i_se_e8mf4:
8436+
case Intrinsic::riscv_sf_vc_i_se_e8mf2:
8437+
case Intrinsic::riscv_sf_vc_i_se_e8m1:
8438+
case Intrinsic::riscv_sf_vc_i_se_e8m2:
8439+
case Intrinsic::riscv_sf_vc_i_se_e8m4:
8440+
case Intrinsic::riscv_sf_vc_i_se_e8m8:
8441+
case Intrinsic::riscv_sf_vc_i_se_e16mf4:
8442+
case Intrinsic::riscv_sf_vc_i_se_e16mf2:
8443+
case Intrinsic::riscv_sf_vc_i_se_e16m1:
8444+
case Intrinsic::riscv_sf_vc_i_se_e16m2:
8445+
case Intrinsic::riscv_sf_vc_i_se_e16m4:
8446+
case Intrinsic::riscv_sf_vc_i_se_e16m8:
8447+
case Intrinsic::riscv_sf_vc_i_se_e32mf2:
8448+
case Intrinsic::riscv_sf_vc_i_se_e32m1:
8449+
case Intrinsic::riscv_sf_vc_i_se_e32m2:
8450+
case Intrinsic::riscv_sf_vc_i_se_e32m4:
8451+
case Intrinsic::riscv_sf_vc_i_se_e32m8:
8452+
case Intrinsic::riscv_sf_vc_i_se_e64m1:
8453+
case Intrinsic::riscv_sf_vc_i_se_e64m2:
8454+
case Intrinsic::riscv_sf_vc_i_se_e64m4:
8455+
case Intrinsic::riscv_sf_vc_i_se_e64m8:
8456+
case Intrinsic::riscv_sf_vc_xv_se:
8457+
case Intrinsic::riscv_sf_vc_iv_se:
8458+
case Intrinsic::riscv_sf_vc_vv_se:
8459+
case Intrinsic::riscv_sf_vc_fv_se:
8460+
case Intrinsic::riscv_sf_vc_xvv_se:
8461+
case Intrinsic::riscv_sf_vc_ivv_se:
8462+
case Intrinsic::riscv_sf_vc_vvv_se:
8463+
case Intrinsic::riscv_sf_vc_fvv_se:
8464+
case Intrinsic::riscv_sf_vc_xvw_se:
8465+
case Intrinsic::riscv_sf_vc_ivw_se:
8466+
case Intrinsic::riscv_sf_vc_vvw_se:
8467+
case Intrinsic::riscv_sf_vc_fvw_se: {
8468+
if (!llvm::any_of(Op->op_values(), [&](const SDValue &V) {
8469+
return V.getValueType().isFixedLengthVector();
8470+
}))
8471+
break;
8472+
8473+
SmallVector<SDValue, 6> Ops;
8474+
for (const SDValue &V : Op->op_values()) {
8475+
// Skip non-fixed vector operands.
8476+
if (!V.getValueType().isFixedLengthVector()) {
8477+
Ops.push_back(V);
8478+
continue;
8479+
}
8480+
8481+
MVT OpContainerVT =
8482+
getContainerForFixedLengthVector(V.getSimpleValueType());
8483+
Ops.push_back(convertToScalableVector(OpContainerVT, V, DAG, Subtarget));
8484+
}
8485+
8486+
return DAG.getNode(ISD::INTRINSIC_VOID, SDLoc(Op), Op->getVTList(), Ops);
8487+
}
83358488
}
83368489

83378490
return lowerVectorIntrinsicScalars(Op, DAG, Subtarget);

0 commit comments

Comments
 (0)