Skip to content

Commit 70553eb

Browse files
MaskRayMaskRay
committed
[𝘀𝗽𝗿] initial version
Created using spr 1.3.5-bogner
1 parent 4ff98fd commit 70553eb

File tree

9 files changed

+92
-131
lines changed

9 files changed

+92
-131
lines changed

‎bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -435,19 +435,19 @@ class RISCVMCPlusBuilder : public MCPlusBuilder {
435435
case ELF::R_RISCV_TLS_GD_HI20:
436436
// The GOT is reused so no need to create GOT relocations
437437
case ELF::R_RISCV_PCREL_HI20:
438-
return RISCVMCExpr::create(Expr, RISCVMCExpr::VK_PCREL_HI, Ctx);
438+
return RISCVMCExpr::create(Expr, ELF::R_RISCV_PCREL_HI20, Ctx);
439439
case ELF::R_RISCV_PCREL_LO12_I:
440440
case ELF::R_RISCV_PCREL_LO12_S:
441441
return RISCVMCExpr::create(Expr, RISCVMCExpr::VK_PCREL_LO, Ctx);
442442
case ELF::R_RISCV_HI20:
443-
return RISCVMCExpr::create(Expr, RISCVMCExpr::VK_HI, Ctx);
443+
return RISCVMCExpr::create(Expr, ELF::R_RISCV_HI20, Ctx);
444444
case ELF::R_RISCV_LO12_I:
445445
case ELF::R_RISCV_LO12_S:
446446
return RISCVMCExpr::create(Expr, RISCVMCExpr::VK_LO, Ctx);
447447
case ELF::R_RISCV_CALL:
448448
return RISCVMCExpr::create(Expr, RISCVMCExpr::VK_CALL, Ctx);
449449
case ELF::R_RISCV_CALL_PLT:
450-
return RISCVMCExpr::create(Expr, RISCVMCExpr::VK_CALL_PLT, Ctx);
450+
return RISCVMCExpr::create(Expr, ELF::R_RISCV_CALL_PLT, Ctx);
451451
}
452452
}
453453

@@ -473,7 +473,7 @@ class RISCVMCPlusBuilder : public MCPlusBuilder {
473473
default:
474474
return false;
475475
case RISCVMCExpr::VK_CALL:
476-
case RISCVMCExpr::VK_CALL_PLT:
476+
case ELF::R_RISCV_CALL_PLT:
477477
return true;
478478
}
479479
}

‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp‎

Lines changed: 15 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -583,7 +583,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
583583

584584
RISCVMCExpr::Specifier VK = RISCVMCExpr::VK_None;
585585
return RISCVAsmParser::classifySymbolRef(getImm(), VK) &&
586-
(VK == RISCVMCExpr::VK_CALL || VK == RISCVMCExpr::VK_CALL_PLT);
586+
(VK == RISCVMCExpr::VK_CALL || VK == ELF::R_RISCV_CALL_PLT);
587587
}
588588

589589
bool isPseudoJumpSymbol() const {
@@ -605,7 +605,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
605605

606606
RISCVMCExpr::Specifier VK = RISCVMCExpr::VK_None;
607607
return RISCVAsmParser::classifySymbolRef(getImm(), VK) &&
608-
VK == RISCVMCExpr::VK_TPREL_ADD;
608+
VK == ELF::R_RISCV_TPREL_ADD;
609609
}
610610

611611
bool isTLSDESCCallSymbol() const {
@@ -616,7 +616,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
616616

617617
RISCVMCExpr::Specifier VK = RISCVMCExpr::VK_None;
618618
return RISCVAsmParser::classifySymbolRef(getImm(), VK) &&
619-
VK == RISCVMCExpr::VK_TLSDESC_CALL;
619+
VK == ELF::R_RISCV_TLSDESC_CALL;
620620
}
621621

622622
bool isCSRSystemRegister() const { return isSystemRegister(); }
@@ -868,8 +868,8 @@ struct RISCVOperand final : public MCParsedAsmOperand {
868868
return RISCVAsmParser::classifySymbolRef(getImm(), VK) &&
869869
(VK == RISCVMCExpr::VK_LO || VK == RISCVMCExpr::VK_PCREL_LO ||
870870
VK == RISCVMCExpr::VK_TPREL_LO ||
871-
VK == RISCVMCExpr::VK_TLSDESC_LOAD_LO ||
872-
VK == RISCVMCExpr::VK_TLSDESC_ADD_LO);
871+
VK == ELF::R_RISCV_TLSDESC_LOAD_LO12 ||
872+
VK == ELF::R_RISCV_TLSDESC_ADD_LO12);
873873
}
874874

875875
bool isSImm12Lsb00000() const {
@@ -912,7 +912,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
912912

913913
RISCVMCExpr::Specifier VK = RISCVMCExpr::VK_None;
914914
return RISCVAsmParser::classifySymbolRef(getImm(), VK) &&
915-
(VK == RISCVMCExpr::VK_HI || VK == RISCVMCExpr::VK_TPREL_HI);
915+
(VK == ELF::R_RISCV_HI20 || VK == ELF::R_RISCV_TPREL_HI20);
916916
}
917917

918918
bool isUImm20AUIPC() const {
@@ -925,10 +925,9 @@ struct RISCVOperand final : public MCParsedAsmOperand {
925925

926926
RISCVMCExpr::Specifier VK = RISCVMCExpr::VK_None;
927927
return RISCVAsmParser::classifySymbolRef(getImm(), VK) &&
928-
(VK == RISCVMCExpr::VK_PCREL_HI || VK == RISCVMCExpr::VK_GOT_HI ||
929-
VK == RISCVMCExpr::VK_TLS_GOT_HI ||
930-
VK == RISCVMCExpr::VK_TLS_GD_HI ||
931-
VK == RISCVMCExpr::VK_TLSDESC_HI);
928+
(VK == ELF::R_RISCV_PCREL_HI20 || VK == ELF::R_RISCV_GOT_HI20 ||
929+
VK == ELF::R_RISCV_TLS_GOT_HI20 || VK == ELF::R_RISCV_TLS_GD_HI20 ||
930+
VK == ELF::R_RISCV_TLSDESC_HI20);
932931
}
933932

934933
bool isImmZero() const {
@@ -2168,7 +2167,7 @@ ParseStatus RISCVAsmParser::parseCallSymbol(OperandVector &Operands) {
21682167
}
21692168

21702169
SMLoc E = SMLoc::getFromPointer(S.getPointer() + Identifier.size());
2171-
RISCVMCExpr::Specifier Kind = RISCVMCExpr::VK_CALL_PLT;
2170+
RISCVMCExpr::Specifier Kind = ELF::R_RISCV_CALL_PLT;
21722171

21732172
MCSymbol *Sym = getContext().getOrCreateSymbol(Identifier);
21742173
Res = MCSymbolRefExpr::create(Sym, getContext());
@@ -3409,7 +3408,7 @@ void RISCVAsmParser::emitLoadLocalAddress(MCInst &Inst, SMLoc IDLoc,
34093408
// ADDI rdest, rdest, %pcrel_lo(TmpLabel)
34103409
MCRegister DestReg = Inst.getOperand(0).getReg();
34113410
const MCExpr *Symbol = Inst.getOperand(1).getExpr();
3412-
emitAuipcInstPair(DestReg, DestReg, Symbol, RISCVMCExpr::VK_PCREL_HI,
3411+
emitAuipcInstPair(DestReg, DestReg, Symbol, ELF::R_RISCV_PCREL_HI20,
34133412
RISCV::ADDI, IDLoc, Out);
34143413
}
34153414

@@ -3424,7 +3423,7 @@ void RISCVAsmParser::emitLoadGlobalAddress(MCInst &Inst, SMLoc IDLoc,
34243423
MCRegister DestReg = Inst.getOperand(0).getReg();
34253424
const MCExpr *Symbol = Inst.getOperand(1).getExpr();
34263425
unsigned SecondOpcode = isRV64() ? RISCV::LD : RISCV::LW;
3427-
emitAuipcInstPair(DestReg, DestReg, Symbol, RISCVMCExpr::VK_GOT_HI,
3426+
emitAuipcInstPair(DestReg, DestReg, Symbol, ELF::R_RISCV_GOT_HI20,
34283427
SecondOpcode, IDLoc, Out);
34293428
}
34303429

@@ -3454,7 +3453,7 @@ void RISCVAsmParser::emitLoadTLSIEAddress(MCInst &Inst, SMLoc IDLoc,
34543453
MCRegister DestReg = Inst.getOperand(0).getReg();
34553454
const MCExpr *Symbol = Inst.getOperand(1).getExpr();
34563455
unsigned SecondOpcode = isRV64() ? RISCV::LD : RISCV::LW;
3457-
emitAuipcInstPair(DestReg, DestReg, Symbol, RISCVMCExpr::VK_TLS_GOT_HI,
3456+
emitAuipcInstPair(DestReg, DestReg, Symbol, ELF::R_RISCV_TLS_GOT_HI20,
34583457
SecondOpcode, IDLoc, Out);
34593458
}
34603459

@@ -3468,7 +3467,7 @@ void RISCVAsmParser::emitLoadTLSGDAddress(MCInst &Inst, SMLoc IDLoc,
34683467
// ADDI rdest, rdest, %pcrel_lo(TmpLabel)
34693468
MCRegister DestReg = Inst.getOperand(0).getReg();
34703469
const MCExpr *Symbol = Inst.getOperand(1).getExpr();
3471-
emitAuipcInstPair(DestReg, DestReg, Symbol, RISCVMCExpr::VK_TLS_GD_HI,
3470+
emitAuipcInstPair(DestReg, DestReg, Symbol, ELF::R_RISCV_TLS_GD_HI20,
34723471
RISCV::ADDI, IDLoc, Out);
34733472
}
34743473

@@ -3494,7 +3493,7 @@ void RISCVAsmParser::emitLoadStoreSymbol(MCInst &Inst, unsigned Opcode,
34943493
}
34953494

34963495
const MCExpr *Symbol = Inst.getOperand(SymbolOpIdx).getExpr();
3497-
emitAuipcInstPair(DestReg, TmpReg, Symbol, RISCVMCExpr::VK_PCREL_HI, Opcode,
3496+
emitAuipcInstPair(DestReg, TmpReg, Symbol, ELF::R_RISCV_PCREL_HI20, Opcode,
34983497
IDLoc, Out);
34993498
}
35003499

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp‎

Lines changed: 12 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -54,15 +54,15 @@ unsigned RISCVELFObjectWriter::getRelocType(MCContext &Ctx,
5454
unsigned Kind = Fixup.getTargetKind();
5555
auto Spec = RISCVMCExpr::Specifier(Target.getSpecifier());
5656
switch (Spec) {
57-
case RISCVMCExpr::VK_TPREL_HI:
58-
case RISCVMCExpr::VK_TLS_GOT_HI:
59-
case RISCVMCExpr::VK_TLS_GD_HI:
60-
case RISCVMCExpr::VK_TLSDESC_HI:
57+
case ELF::R_RISCV_TPREL_HI20:
58+
case ELF::R_RISCV_TLS_GOT_HI20:
59+
case ELF::R_RISCV_TLS_GD_HI20:
60+
case ELF::R_RISCV_TLSDESC_HI20:
6161
if (auto *SA = Target.getAddSym())
6262
cast<MCSymbolELF>(SA)->setType(ELF::STT_TLS);
6363
break;
64-
case RISCVMCExpr::VK_PLTPCREL:
65-
case RISCVMCExpr::VK_GOTPCREL:
64+
case ELF::R_RISCV_PLT32:
65+
case ELF::R_RISCV_GOT32_PCREL:
6666
if (Kind == FK_Data_4)
6767
break;
6868
Ctx.reportError(Fixup.getLoc(),
@@ -124,15 +124,12 @@ unsigned RISCVELFObjectWriter::getRelocType(MCContext &Ctx,
124124
return ELF::R_RISCV_NONE;
125125
case FK_Data_4:
126126
if (Expr->getKind() == MCExpr::Target) {
127-
switch (cast<RISCVMCExpr>(Expr)->getSpecifier()) {
128-
case RISCVMCExpr::VK_32_PCREL:
129-
return ELF::R_RISCV_32_PCREL;
130-
case RISCVMCExpr::VK_GOTPCREL:
131-
return ELF::R_RISCV_GOT32_PCREL;
132-
case RISCVMCExpr::VK_PLTPCREL:
133-
return ELF::R_RISCV_PLT32;
134-
default:
135-
break;
127+
auto Spec = cast<RISCVMCExpr>(Expr)->getSpecifier();
128+
switch (Spec) {
129+
case ELF::R_RISCV_32_PCREL:
130+
case ELF::R_RISCV_GOT32_PCREL:
131+
case ELF::R_RISCV_PLT32:
132+
return Spec;
136133
}
137134
}
138135
return ELF::R_RISCV_32;

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.cpp‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,7 @@
1313
#include "RISCVMCAsmInfo.h"
1414
#include "MCTargetDesc/RISCVMCExpr.h"
1515
#include "llvm/BinaryFormat/Dwarf.h"
16+
#include "llvm/BinaryFormat/ELF.h"
1617
#include "llvm/MC/MCExpr.h"
1718
#include "llvm/MC/MCStreamer.h"
1819
#include "llvm/TargetParser/Triple.h"
@@ -44,5 +45,5 @@ const MCExpr *RISCVMCAsmInfo::getExprForFDESymbol(const MCSymbol *Sym,
4445
MCContext &Ctx = Streamer.getContext();
4546
const MCExpr *ME = MCSymbolRefExpr::create(Sym, Ctx);
4647
assert(Encoding & dwarf::DW_EH_PE_sdata4 && "Unexpected encoding");
47-
return RISCVMCExpr::create(ME, RISCVMCExpr::VK_32_PCREL, Ctx);
48+
return RISCVMCExpr::create(ME, ELF::R_RISCV_32_PCREL, Ctx);
4849
}

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp‎

Lines changed: 12 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -206,7 +206,7 @@ void RISCVMCCodeEmitter::expandAddTPRel(const MCInst &MI,
206206
"Expected expression as third input to TP-relative add");
207207

208208
const RISCVMCExpr *Expr = dyn_cast<RISCVMCExpr>(SrcSymbol.getExpr());
209-
assert(Expr && Expr->getSpecifier() == RISCVMCExpr::VK_TPREL_ADD &&
209+
assert(Expr && Expr->getSpecifier() == ELF::R_RISCV_TPREL_ADD &&
210210
"Expected tprel_add relocation on TP-relative symbol");
211211

212212
// Emit the correct tprel_add relocation for the symbol.
@@ -573,20 +573,19 @@ uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
573573
bool RelaxCandidate = false;
574574
if (Kind == MCExpr::Target) {
575575
const RISCVMCExpr *RVExpr = cast<RISCVMCExpr>(Expr);
576-
576+
FixupKind = RVExpr->getSpecifier();
577577
switch (RVExpr->getSpecifier()) {
578-
case RISCVMCExpr::VK_None:
579-
case RISCVMCExpr::VK_32_PCREL:
580-
case RISCVMCExpr::VK_GOTPCREL:
581-
case RISCVMCExpr::VK_PLTPCREL:
582-
llvm_unreachable("unhandled specifier");
583-
case RISCVMCExpr::VK_TPREL_ADD:
578+
default:
579+
assert(FixupKind && FixupKind < FirstTargetFixupKind &&
580+
"invalid specifier");
581+
break;
582+
case ELF::R_RISCV_TPREL_ADD:
584583
// tprel_add is only used to indicate that a relocation should be emitted
585584
// for an add instruction used in TP-relative addressing. It should not be
586585
// expanded as if representing an actual instruction operand and so to
587586
// encounter it here is an error.
588587
llvm_unreachable(
589-
"VK_TPREL_ADD should not represent an instruction operand");
588+
"ELF::R_RISCV_TPREL_ADD should not represent an instruction operand");
590589
case RISCVMCExpr::VK_LO:
591590
if (MIFrm == RISCVII::InstFormatI)
592591
FixupKind = RISCV::fixup_riscv_lo12_i;
@@ -596,7 +595,7 @@ uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
596595
llvm_unreachable("VK_LO used with unexpected instruction format");
597596
RelaxCandidate = true;
598597
break;
599-
case RISCVMCExpr::VK_HI:
598+
case ELF::R_RISCV_HI20:
600599
FixupKind = RISCV::fixup_riscv_hi20;
601600
RelaxCandidate = true;
602601
break;
@@ -609,13 +608,10 @@ uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
609608
llvm_unreachable("VK_PCREL_LO used with unexpected instruction format");
610609
RelaxCandidate = true;
611610
break;
612-
case RISCVMCExpr::VK_PCREL_HI:
611+
case ELF::R_RISCV_PCREL_HI20:
613612
FixupKind = RISCV::fixup_riscv_pcrel_hi20;
614613
RelaxCandidate = true;
615614
break;
616-
case RISCVMCExpr::VK_GOT_HI:
617-
FixupKind = ELF::R_RISCV_GOT_HI20;
618-
break;
619615
case RISCVMCExpr::VK_TPREL_LO:
620616
if (MIFrm == RISCVII::InstFormatI)
621617
FixupKind = ELF::R_RISCV_TPREL_LO12_I;
@@ -625,36 +621,17 @@ uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
625621
llvm_unreachable("VK_TPREL_LO used with unexpected instruction format");
626622
RelaxCandidate = true;
627623
break;
628-
case RISCVMCExpr::VK_TPREL_HI:
629-
FixupKind = ELF::R_RISCV_TPREL_HI20;
624+
case ELF::R_RISCV_TPREL_HI20:
630625
RelaxCandidate = true;
631626
break;
632-
case RISCVMCExpr::VK_TLS_GOT_HI:
633-
FixupKind = ELF::R_RISCV_TLS_GOT_HI20;
634-
break;
635-
case RISCVMCExpr::VK_TLS_GD_HI:
636-
FixupKind = ELF::R_RISCV_TLS_GD_HI20;
637-
break;
638627
case RISCVMCExpr::VK_CALL:
639628
FixupKind = RISCV::fixup_riscv_call;
640629
RelaxCandidate = true;
641630
break;
642-
case RISCVMCExpr::VK_CALL_PLT:
631+
case ELF::R_RISCV_CALL_PLT:
643632
FixupKind = RISCV::fixup_riscv_call_plt;
644633
RelaxCandidate = true;
645634
break;
646-
case RISCVMCExpr::VK_TLSDESC_HI:
647-
FixupKind = ELF::R_RISCV_TLSDESC_HI20;
648-
break;
649-
case RISCVMCExpr::VK_TLSDESC_LOAD_LO:
650-
FixupKind = ELF::R_RISCV_TLSDESC_LOAD_LO12;
651-
break;
652-
case RISCVMCExpr::VK_TLSDESC_ADD_LO:
653-
FixupKind = ELF::R_RISCV_TLSDESC_ADD_LO12;
654-
break;
655-
case RISCVMCExpr::VK_TLSDESC_CALL:
656-
FixupKind = ELF::R_RISCV_TLSDESC_CALL;
657-
break;
658635
case RISCVMCExpr::VK_QC_ABS20:
659636
FixupKind = RISCV::fixup_riscv_qc_abs20_u;
660637
break;

0 commit comments

Comments
 (0)