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[AArch64][llvm] Add support for Permission Overlays Extension 2 (FEAT_S1POE2)
Add assembly/disassembly support for AArch64 FEAT_S1POE2 (Stage 1 Permission Overlays Extension 2), as documented here: https://developer.arm.com/documentation/109697/2025_09/Future-Architecture-Technologies Co-authored-by: Rodolfo Wottrich <[email protected]>
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‎clang/test/Driver/aarch64-vfat.c‎

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@@ -5,3 +5,15 @@
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// RUN: %clang -target aarch64 -march=armv9.7a+mops-go -### -c %s 2>&1 | FileCheck -check-prefix=VFAT-MOPS-GO %s
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// RUN: %clang -target aarch64 -march=armv9.7-a+mops-go -### -c %s 2>&1 | FileCheck -check-prefix=VFAT-MOPS-GO %s
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// VFAT-MOPS-GO: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.7a"{{.*}} "-target-feature" "+mops-go"
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// RUN: %clang -target aarch64 -march=armv9.7a+poe2 -### -c %s 2>&1 | FileCheck -check-prefix=VFAT-POE2 %s
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// RUN: %clang -target aarch64 -march=armv9.7-a+poe2 -### -c %s 2>&1 | FileCheck -check-prefix=VFAT-POE2 %s
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// VFAT-POE2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.7a"{{.*}} "-target-feature" "+poe2"
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// RUN: %clang -target aarch64 -march=armv9.7a+tev -### -c %s 2>&1 | FileCheck -check-prefix=VFAT-TEV %s
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// RUN: %clang -target aarch64 -march=armv9.7-a+tev -### -c %s 2>&1 | FileCheck -check-prefix=VFAT-TEV %s
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// VFAT-TEV: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.7a"{{.*}} "-target-feature" "+tev"
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// RUN: %clang -target aarch64 -march=armv9.7a+btie -### -c %s 2>&1 | FileCheck -check-prefix=VFAT-BTIE %s
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// RUN: %clang -target aarch64 -march=armv9.7-a+btie -### -c %s 2>&1 | FileCheck -check-prefix=VFAT-BTIE %s
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// VFAT-BTIE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.7a"{{.*}} "-target-feature" "+btie"

‎clang/test/Driver/print-supported-extensions-aarch64.c‎

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@@ -8,6 +8,7 @@
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// CHECK-NEXT: bf16 FEAT_BF16 Enable BFloat16 Extension
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// CHECK-NEXT: brbe FEAT_BRBE Enable Branch Record Buffer Extension
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// CHECK-NEXT: bti FEAT_BTI Enable Branch Target Identification
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// CHECK-NEXT: btie FEAT_BTIE Enable Enhanced Branch Target Identification extension
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// CHECK-NEXT: cmh FEAT_CMH Enable Armv9.7-A Contention Management Hints
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// CHECK-NEXT: cmpbr FEAT_CMPBR Enable Armv9.6-A base compare and branch instructions
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// CHECK-NEXT: fcma FEAT_FCMA Enable Armv8.3-A Floating-point complex number support
@@ -59,6 +60,7 @@
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// CHECK-NEXT: pauth-lr FEAT_PAuth_LR Enable Armv9.5-A PAC enhancements
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// CHECK-NEXT: pcdphint FEAT_PCDPHINT Enable Armv9.6-A Producer Consumer Data Placement hints
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// CHECK-NEXT: pmuv3 FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
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// CHECK-NEXT: poe2 FEAT_S1POE2 Enable Stage 1 Permission Overlays Extension 2 instructions
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// CHECK-NEXT: pops FEAT_PoPS Enable Armv9.6-A Point Of Physical Storage (PoPS) DC instructions
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// CHECK-NEXT: predres FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions
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// CHECK-NEXT: rng FEAT_RNG Enable Random Number generation instructions
@@ -113,6 +115,7 @@
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// CHECK-NEXT: sve2p1 FEAT_SVE2p1 Enable Scalable Vector Extension 2.1 instructions
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// CHECK-NEXT: sve2p2 FEAT_SVE2p2 Enable Armv9.6-A Scalable Vector Extension 2.2 instructions
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// CHECK-NEXT: sve2p3 FEAT_SVE2p3 Enable Armv9.7-A Scalable Vector Extension 2.3 instructions
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// CHECK-NEXT: tev FEAT_TEV Enable TIndex Exception-like Vector instructions
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// CHECK-NEXT: the FEAT_THE Enable Armv8.9-A Translation Hardening Extension
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// CHECK-NEXT: tlbid FEAT_TLBID Enable Armv9.7-A TLBI Domains extension
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// CHECK-NEXT: tlbiw FEAT_TLBIW Enable Armv9.5-A TLBI VMALL for Dirty State

‎llvm/lib/Target/AArch64/AArch64Features.td‎

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@@ -632,6 +632,15 @@ def FeatureF16F32MM : ExtensionWithMArch<"f16f32mm", "F16F32MM", "FEAT_F16F32MM"
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def FeatureMOPS_GO: ExtensionWithMArch<"mops-go", "MOPS_GO", "FEAT_MOPS_GO",
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"Enable memset acceleration granule only">;
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def FeatureBTIE: ExtensionWithMArch<"btie", "BTIE", "FEAT_BTIE",
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"Enable Enhanced Branch Target Identification extension">;
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def FeatureS1POE2: ExtensionWithMArch<"poe2", "POE2", "FEAT_S1POE2",
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"Enable Stage 1 Permission Overlays Extension 2 instructions", [FeatureBTIE]>;
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def FeatureTEV: ExtensionWithMArch<"tev", "TEV", "FEAT_TEV",
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"Enable TIndex Exception-like Vector instructions">;
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//===----------------------------------------------------------------------===//
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// Other Features
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//===----------------------------------------------------------------------===//

‎llvm/lib/Target/AArch64/AArch64InstrFormats.td‎

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@@ -1909,6 +1909,21 @@ def CMHPriorityHint_op : Operand<i32> {
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}];
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}
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def TIndexHintOperand : AsmOperandClass {
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let Name = "TIndexHint";
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let ParserMethod = "tryParseTIndexHint";
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}
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def TIndexhint_op : Operand<i32> {
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let ParserMatchClass = TIndexHintOperand;
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let PrintMethod = "printTIndexHintOp";
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let MCOperandPredicate = [{
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if (!MCOp.isImm())
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return false;
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return AArch64TIndexHint::lookupTIndexByEncoding(MCOp.getImm()) != nullptr;
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}];
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}
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class MRSI : RtSystemI<1, (outs GPR64:$Rt), (ins mrs_sysreg_op:$systemreg),
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"mrs", "\t$Rt, $systemreg"> {
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bits<16> systemreg;
@@ -13366,3 +13381,86 @@ class STCPHInst<string asm> : I<
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let Inst{7-5} = 0b100;
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let Inst{4-0} = 0b11111;
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}
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//---
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// Permission Overlays Extension 2 (FEAT_S1POE2)
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//---
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class TCHANGERegInst<string asm, bit isB> : I<
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(outs GPR64:$Xd),
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(ins GPR64:$Xn, TIndexhint_op:$nb),
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asm, "\t$Xd, $Xn, $nb", "", []>, Sched<[]> {
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bits<5> Xd;
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bits<5> Xn;
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bits<1> nb;
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let Inst{31-19} = 0b1101010110000;
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let Inst{18} = isB;
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let Inst{17} = nb;
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let Inst{16-10} = 0b0000000;
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let Inst{9-5} = Xn;
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let Inst{4-0} = Xd;
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}
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class TCHANGEImmInst<string asm, bit isB> : I<
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(outs GPR64:$Xd),
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(ins imm0_127:$imm, TIndexhint_op:$nb),
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asm, "\t$Xd, $imm, $nb", "", []>, Sched<[]> {
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bits<5> Xd;
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bits<7> imm;
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bits<1> nb;
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let Inst{31-19} = 0b1101010110010;
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let Inst{18} = isB;
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let Inst{17} = nb;
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let Inst{16-12} = 0b00000;
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let Inst{11-5} = imm;
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let Inst{4-0} = Xd;
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}
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class TENTERInst<string asm> : I<
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(outs),
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(ins imm0_127:$imm, TIndexhint_op:$nb),
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asm, "\t$imm, $nb", "", []>, Sched<[]> {
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bits<7> imm;
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bits<1> nb;
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let Inst{31-20} = 0b110101001110;
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let Inst{19-18} = 0b00;
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let Inst{17} = nb;
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let Inst{16-12} = 0b00000;
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let Inst{11-5} = imm;
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let Inst{4-0} = 0b00000;
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}
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class TEXITInst<string asm> : I<
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(outs),
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(ins TIndexhint_op:$nb),
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asm, "\t$nb", "", []>, Sched<[]> {
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bits<1> nb;
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let Inst{31-13} = 0b1101011011111111000;
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let Inst{12-11} = 0b00;
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let Inst{10} = nb;
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let Inst{9-0} = 0b1111100000;
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}
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multiclass TCHANGEReg<string asm , bit isB> {
13446+
def NAME : TCHANGERegInst<asm, isB>;
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def : InstAlias<asm # "\t$Xd, $Xn",
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(!cast<Instruction>(NAME) GPR64:$Xd, GPR64:$Xn, 0), 1>;
13449+
}
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multiclass TCHANGEImm<string asm, bit isB> {
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def NAME : TCHANGEImmInst<asm, isB>;
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def : InstAlias<asm # "\t$Xd, $Xn",
13454+
(!cast<Instruction>(NAME) GPR64:$Xd, imm0_127:$Xn, 0), 1>;
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}
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multiclass TENTER<string asm> {
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def NAME : TENTERInst<asm>;
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def : InstAlias<asm # "\t$imm",
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(!cast<Instruction>(NAME) imm0_127:$imm, 0), 1>;
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}
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multiclass TEXIT<string asm> {
13464+
def NAME : TEXITInst<asm>;
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def : InstAlias<asm, (!cast<Instruction>(NAME) 0), 1>;
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}

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td‎

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@@ -346,6 +346,8 @@ def HasCCDP : Predicate<"Subtarget->hasCCDP()">,
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AssemblerPredicateWithAll<(all_of FeatureCacheDeepPersist), "ccdp">;
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def HasBTI : Predicate<"Subtarget->hasBTI()">,
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AssemblerPredicateWithAll<(all_of FeatureBranchTargetId), "bti">;
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def HasBTIE : Predicate<"Subtarget->hasBTIE()">,
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AssemblerPredicateWithAll<(all_of FeatureBTIE), "btie">;
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def HasMTE : Predicate<"Subtarget->hasMTE()">,
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AssemblerPredicateWithAll<(all_of FeatureMTE), "mte">;
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def HasTME : Predicate<"Subtarget->hasTME()">,
@@ -407,6 +409,10 @@ def HasGCIE : Predicate<"Subtarget->hasGCIE()">,
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AssemblerPredicateWithAll<(all_of FeatureGCIE), "gcie">;
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def HasMOPS_GO : Predicate<"Subtarget->hasMOPS_GO()">,
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AssemblerPredicateWithAll<(all_of FeatureMOPS_GO), "mops-go">;
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def HasS1POE2 : Predicate<"Subtarget->hasS1POE2()">,
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AssemblerPredicateWithAll<(all_of FeatureS1POE2), "poe2">;
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def HasTEV : Predicate<"Subtarget->hasTEV()">,
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AssemblerPredicateWithAll<(all_of FeatureTEV), "tev">;
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def IsLE : Predicate<"Subtarget->isLittleEndian()">;
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def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
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def IsWindows : Predicate<"Subtarget->isTargetWindows()">;
@@ -1542,6 +1548,7 @@ let Predicates = [HasPCDPHINT] in {
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// should not emit these mnemonics unless BTI is enabled.
15431549
def : InstAlias<"bti", (HINT 32), 0>;
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def : InstAlias<"bti $op", (HINT btihint_op:$op), 0>;
1551+
def : InstAlias<"bti r", (HINT 32)>, Requires<[HasBTIE]>;
15451552
def : InstAlias<"bti", (HINT 32)>, Requires<[HasBTI]>;
15461553
def : InstAlias<"bti $op", (HINT btihint_op:$op)>, Requires<[HasBTI]>;
15471554

@@ -11444,6 +11451,26 @@ let Predicates = [HasCMH] in {
1144411451
def STCPH : STCPHInst<"stcph">; // Store Concurrent Priority Hint instruction
1144511452
}
1144611453

11454+
//===----------------------------------------------------------------------===//
11455+
// Permission Overlays Extension 2 (FEAT_S1POE2)
11456+
//===----------------------------------------------------------------------===//
11457+
11458+
let Predicates = [HasS1POE2] in {
11459+
defm TCHANGEBrr : TCHANGEReg<"tchangeb", true>;
11460+
defm TCHANGEFrr : TCHANGEReg<"tchangef", false>;
11461+
defm TCHANGEBri : TCHANGEImm<"tchangeb", true>;
11462+
defm TCHANGEFri : TCHANGEImm<"tchangef", false>;
11463+
}
11464+
11465+
//===----------------------------------------------------------------------===//
11466+
// TIndex Exception-like Vector (FEAT_TEV)
11467+
//===----------------------------------------------------------------------===//
11468+
11469+
let Predicates = [HasTEV] in {
11470+
defm TENTER : TENTER<"tenter">;
11471+
defm TEXIT : TEXIT<"texit">;
11472+
}
11473+
1144711474
include "AArch64InstrAtomics.td"
1144811475
include "AArch64SVEInstrInfo.td"
1144911476
include "AArch64SMEInstrInfo.td"

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