We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
There was an error while loading. Please reload this page.
1 parent 028a2b4 commit 7072760Copy full SHA for 7072760
llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
@@ -280,7 +280,7 @@ Instruction *InstCombinerImpl::visitMul(BinaryOperator &I) {
280
/*isExact=*/true);
281
282
auto *NewAdd = BinaryOperator::CreateAdd(NewOp, BinOp);
283
- if (HasNSW && (OpBO->getOpcode() == Instruction::LShr ||
+ if (HasNSW && (HasNUW || OpBO->getOpcode() == Instruction::LShr ||
284
ShiftC->getZExtValue() < BitWidth - 1))
285
NewAdd->setHasNoSignedWrap(true);
286
0 commit comments