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spallspall
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make clang format happy
1 parent cb1f55c commit 70734ce

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3 files changed

+71
-69
lines changed

3 files changed

+71
-69
lines changed

‎clang/lib/CodeGen/CGBuiltin.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -18744,7 +18744,7 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned BuiltinID,
1874418744
Value *X = EmitScalarExpr(E->getArg(0));
1874518745

1874618746
return Builder.CreateIntrinsic(
18747-
/*ReturnType=*/ConvertType(E->getType()),
18747+
/*ReturnType=*/ConvertType(E->getType()),
1874818748
getFirstBitHighIntrinsic(CGM.getHLSLRuntime(), E->getArg(0)->getType()),
1874918749
ArrayRef<Value *>{X}, nullptr, "hlsl.firstbithigh");
1875018750
}

‎clang/lib/Sema/SemaHLSL.cpp‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1939,7 +1939,8 @@ bool SemaHLSL::CheckBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) {
19391939

19401940
if (auto *VecTy = EltTy->getAs<VectorType>()) {
19411941
EltTy = VecTy->getElementType();
1942-
ResTy = SemaRef.Context.getVectorType(ResTy, VecTy->getNumElements(), VecTy->getVectorKind());
1942+
ResTy = SemaRef.Context.getVectorType(ResTy, VecTy->getNumElements(),
1943+
VecTy->getVectorKind());
19431944
}
19441945

19451946
if (!EltTy->isIntegerType()) {

‎llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp‎

Lines changed: 68 additions & 67 deletions
Original file line numberDiff line numberDiff line change
@@ -93,24 +93,24 @@ class SPIRVInstructionSelector : public InstructionSelector {
9393
MachineInstr &I) const;
9494

9595
bool selectFirstBitHigh(Register ResVReg, const SPIRVType *ResType,
96-
MachineInstr &I, bool IsSigned) const;
96+
MachineInstr &I, bool IsSigned) const;
9797

9898
bool selectFirstBitHigh16(Register ResVReg, const SPIRVType *ResType,
99-
MachineInstr &I, bool IsSigned) const;
99+
MachineInstr &I, bool IsSigned) const;
100100

101101
bool selectFirstBitHigh32(Register ResVReg, const SPIRVType *ResType,
102-
MachineInstr &I, Register SrcReg,
103-
bool IsSigned) const;
102+
MachineInstr &I, Register SrcReg,
103+
bool IsSigned) const;
104104

105105
bool selectFirstBitHigh64(Register ResVReg, const SPIRVType *ResType,
106-
MachineInstr &I, bool IsSigned) const;
106+
MachineInstr &I, bool IsSigned) const;
107107

108108
bool selectGlobalValue(Register ResVReg, MachineInstr &I,
109109
const MachineInstr *Init = nullptr) const;
110110

111111
bool selectNAryOpWithSrcs(Register ResVReg, const SPIRVType *ResType,
112-
MachineInstr &I, std::vector<Register> SrcRegs,
113-
unsigned Opcode) const;
112+
MachineInstr &I, std::vector<Register> SrcRegs,
113+
unsigned Opcode) const;
114114

115115
bool selectUnOpWithSrc(Register ResVReg, const SPIRVType *ResType,
116116
MachineInstr &I, Register SrcReg,
@@ -836,14 +836,14 @@ bool SPIRVInstructionSelector::selectExtInst(Register ResVReg,
836836
}
837837

838838
bool SPIRVInstructionSelector::selectNAryOpWithSrcs(Register ResVReg,
839-
const SPIRVType *ResType,
840-
MachineInstr &I,
841-
std::vector<Register> Srcs,
842-
unsigned Opcode) const {
839+
const SPIRVType *ResType,
840+
MachineInstr &I,
841+
std::vector<Register> Srcs,
842+
unsigned Opcode) const {
843843
auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcode))
844-
.addDef(ResVReg)
845-
.addUse(GR.getSPIRVTypeID(ResType));
846-
for(Register SReg : Srcs) {
844+
.addDef(ResVReg)
845+
.addUse(GR.getSPIRVTypeID(ResType));
846+
for (Register SReg : Srcs) {
847847
MIB.addUse(SReg);
848848
}
849849
return MIB.constrainAllUses(TII, TRI, RBI);
@@ -2672,46 +2672,46 @@ Register SPIRVInstructionSelector::buildPointerToResource(
26722672
}
26732673

26742674
bool SPIRVInstructionSelector::selectFirstBitHigh16(Register ResVReg,
2675-
const SPIRVType *ResType,
2676-
MachineInstr &I,
2677-
bool IsSigned) const {
2675+
const SPIRVType *ResType,
2676+
MachineInstr &I,
2677+
bool IsSigned) const {
26782678
unsigned Opcode = IsSigned ? SPIRV::OpSConvert : SPIRV::OpUConvert;
26792679
// zero or sign extend
26802680
Register ExtReg = MRI->createVirtualRegister(GR.getRegClass(ResType));
2681-
bool Result = selectUnOpWithSrc(ExtReg, ResType, I, I.getOperand(2).getReg(),
2682-
Opcode);
2681+
bool Result =
2682+
selectUnOpWithSrc(ExtReg, ResType, I, I.getOperand(2).getReg(), Opcode);
26832683
return Result & selectFirstBitHigh32(ResVReg, ResType, I, ExtReg, IsSigned);
26842684
}
26852685

26862686
bool SPIRVInstructionSelector::selectFirstBitHigh32(Register ResVReg,
2687-
const SPIRVType *ResType,
2688-
MachineInstr &I,
2689-
Register SrcReg,
2690-
bool IsSigned) const {
2687+
const SPIRVType *ResType,
2688+
MachineInstr &I,
2689+
Register SrcReg,
2690+
bool IsSigned) const {
26912691
unsigned Opcode = IsSigned ? GL::FindSMsb : GL::FindUMsb;
26922692
return BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst))
2693-
.addDef(ResVReg)
2694-
.addUse(GR.getSPIRVTypeID(ResType))
2695-
.addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450))
2696-
.addImm(Opcode)
2697-
.addUse(SrcReg)
2698-
.constrainAllUses(TII, TRI, RBI);
2693+
.addDef(ResVReg)
2694+
.addUse(GR.getSPIRVTypeID(ResType))
2695+
.addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450))
2696+
.addImm(Opcode)
2697+
.addUse(SrcReg)
2698+
.constrainAllUses(TII, TRI, RBI);
26992699
}
27002700

27012701
bool SPIRVInstructionSelector::selectFirstBitHigh64(Register ResVReg,
2702-
const SPIRVType *ResType,
2703-
MachineInstr &I,
2704-
bool IsSigned) const {
2702+
const SPIRVType *ResType,
2703+
MachineInstr &I,
2704+
bool IsSigned) const {
27052705
Register OpReg = I.getOperand(2).getReg();
27062706
// 1. split our int64 into 2 pieces using a bitcast
27072707
unsigned count = GR.getScalarOrVectorComponentCount(ResType);
27082708
SPIRVType *baseType = GR.retrieveScalarOrVectorIntType(ResType);
27092709
MachineIRBuilder MIRBuilder(I);
2710-
SPIRVType *postCastT = GR.getOrCreateSPIRVVectorType(baseType, 2 * count,
2711-
MIRBuilder);
2710+
SPIRVType *postCastT =
2711+
GR.getOrCreateSPIRVVectorType(baseType, 2 * count, MIRBuilder);
27122712
Register bitcastReg = MRI->createVirtualRegister(GR.getRegClass(postCastT));
2713-
bool Result = selectUnOpWithSrc(bitcastReg, postCastT, I, OpReg,
2714-
SPIRV::OpBitcast);
2713+
bool Result =
2714+
selectUnOpWithSrc(bitcastReg, postCastT, I, OpReg, SPIRV::OpBitcast);
27152715

27162716
// 2. call firstbithigh
27172717
Register FBHReg = MRI->createVirtualRegister(GR.getRegClass(postCastT));
@@ -2729,76 +2729,77 @@ bool SPIRVInstructionSelector::selectFirstBitHigh64(Register ResVReg,
27292729
// count should be one.
27302730

27312731
Register HighReg = MRI->createVirtualRegister(GR.getRegClass(VResType));
2732-
auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(),
2733-
TII.get(SPIRV::OpVectorShuffle))
2734-
.addDef(HighReg)
2735-
.addUse(GR.getSPIRVTypeID(VResType))
2736-
.addUse(FBHReg)
2737-
.addUse(FBHReg); // this vector will not be selected from; could be empty
2732+
auto MIB =
2733+
BuildMI(*I.getParent(), I, I.getDebugLoc(),
2734+
TII.get(SPIRV::OpVectorShuffle))
2735+
.addDef(HighReg)
2736+
.addUse(GR.getSPIRVTypeID(VResType))
2737+
.addUse(FBHReg)
2738+
.addUse(
2739+
FBHReg); // this vector will not be selected from; could be empty
27382740
unsigned i;
2739-
for(i = 0; i < count*2; i += 2) {
2741+
for (i = 0; i < count * 2; i += 2) {
27402742
MIB.addImm(i);
27412743
}
27422744
Result &= MIB.constrainAllUses(TII, TRI, RBI);
27432745

27442746
// get low bits
27452747
Register LowReg = MRI->createVirtualRegister(GR.getRegClass(VResType));
2746-
MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(),
2747-
TII.get(SPIRV::OpVectorShuffle))
2748-
.addDef(LowReg)
2749-
.addUse(GR.getSPIRVTypeID(VResType))
2750-
.addUse(FBHReg)
2751-
.addUse(FBHReg); // this vector will not be selected from; could be empty
2752-
for(i = 1; i < count*2; i += 2) {
2748+
MIB =
2749+
BuildMI(*I.getParent(), I, I.getDebugLoc(),
2750+
TII.get(SPIRV::OpVectorShuffle))
2751+
.addDef(LowReg)
2752+
.addUse(GR.getSPIRVTypeID(VResType))
2753+
.addUse(FBHReg)
2754+
.addUse(
2755+
FBHReg); // this vector will not be selected from; could be empty
2756+
for (i = 1; i < count * 2; i += 2) {
27532757
MIB.addImm(i);
27542758
}
27552759
Result &= MIB.constrainAllUses(TII, TRI, RBI);
27562760

2757-
SPIRVType *BoolType =
2758-
GR.getOrCreateSPIRVVectorType(GR.getOrCreateSPIRVBoolType(I, TII),
2759-
count,
2760-
MIRBuilder);
2761+
SPIRVType *BoolType = GR.getOrCreateSPIRVVectorType(
2762+
GR.getOrCreateSPIRVBoolType(I, TII), count, MIRBuilder);
27612763
// check if the high bits are == -1;
27622764
Register NegOneReg = GR.getOrCreateConstVector(-1, I, VResType, TII);
27632765
// true if -1
27642766
Register BReg = MRI->createVirtualRegister(GR.getRegClass(BoolType));
27652767
Result &= selectNAryOpWithSrcs(BReg, BoolType, I, {HighReg, NegOneReg},
2766-
SPIRV::OpIEqual);
2768+
SPIRV::OpIEqual);
27672769

27682770
// Select low bits if true in BReg, otherwise high bits
27692771
Register TmpReg = MRI->createVirtualRegister(GR.getRegClass(VResType));
27702772
Result &= selectNAryOpWithSrcs(TmpReg, VResType, I, {BReg, LowReg, HighReg},
2771-
SPIRV::OpSelectVIVCond);
2773+
SPIRV::OpSelectVIVCond);
27722774

27732775
// Add 32 for high bits, 0 for low bits
27742776
Register ValReg = MRI->createVirtualRegister(GR.getRegClass(VResType));
27752777
bool ZeroAsNull = STI.isOpenCLEnv();
27762778
Register Reg32 = GR.getOrCreateConstVector(32, I, VResType, TII, ZeroAsNull);
27772779
Register Reg0 = GR.getOrCreateConstVector(0, I, VResType, TII, ZeroAsNull);
27782780
Result &= selectNAryOpWithSrcs(ValReg, VResType, I, {BReg, Reg0, Reg32},
2779-
SPIRV::OpSelectVIVCond);
2781+
SPIRV::OpSelectVIVCond);
27802782

27812783
Register AddReg = ResVReg;
2782-
if(isScalarRes)
2784+
if (isScalarRes)
27832785
AddReg = MRI->createVirtualRegister(GR.getRegClass(VResType));
27842786
Result &= selectNAryOpWithSrcs(AddReg, VResType, I, {ValReg, TmpReg},
2785-
SPIRV::OpIAddV);
2787+
SPIRV::OpIAddV);
27862788

27872789
// convert result back to scalar if necessary
27882790
if (!isScalarRes)
27892791
return Result;
27902792
else
2791-
return Result & selectNAryOpWithSrcs(ResVReg, ResType, I,
2792-
{AddReg,
2793-
GR.getOrCreateConstInt(0, I, ResType,
2794-
TII)},
2795-
SPIRV::OpVectorExtractDynamic);
2793+
return Result & selectNAryOpWithSrcs(
2794+
ResVReg, ResType, I,
2795+
{AddReg, GR.getOrCreateConstInt(0, I, ResType, TII)},
2796+
SPIRV::OpVectorExtractDynamic);
27962797
}
27972798

27982799
bool SPIRVInstructionSelector::selectFirstBitHigh(Register ResVReg,
2799-
const SPIRVType *ResType,
2800-
MachineInstr &I,
2801-
bool IsSigned) const {
2800+
const SPIRVType *ResType,
2801+
MachineInstr &I,
2802+
bool IsSigned) const {
28022803
// FindUMsb intrinsic only supports 32 bit integers
28032804
Register OpReg = I.getOperand(2).getReg();
28042805
SPIRVType *OpType = GR.getSPIRVTypeForVReg(OpReg);

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