[AArch64][GlobalISel] Add gisel run lines for more MULL tests. NFC

Author: davemgreen

llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll

@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple aarch64-unknown-linux-gnu | FileCheck %s --check-prefixes=CHECK-SD
-; RUN: llc -mtriple=aarch64 -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK-GI
+; RUN: llc -mtriple aarch64-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc -mtriple=aarch64 -global-isel -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI
 
 ; Tests for wider-than-legal extensions into mul/mla.
 
@@ -223,3 +223,5 @@ entry:
   %d = add <16 x i64> %m, %c
   ret <16 x i64> %d
 }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}

llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll

@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -mtriple=arm64-eabi -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
 
 ; rdar://9296808
 ; rdar://9349137
@@ -19,12 +20,24 @@ entry:
 }
 
 define i128 @t2(i64 %a, i64 %b) nounwind readnone ssp {
-; CHECK-LABEL: t2:
-; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mul x8, x0, x1
-; CHECK-NEXT:    smulh x1, x0, x1
-; CHECK-NEXT:    mov x0, x8
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: t2:
+; CHECK-SD:       // %bb.0: // %entry
+; CHECK-SD-NEXT:    mul x8, x0, x1
+; CHECK-SD-NEXT:    smulh x1, x0, x1
+; CHECK-SD-NEXT:    mov x0, x8
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: t2:
+; CHECK-GI:       // %bb.0: // %entry
+; CHECK-GI-NEXT:    asr x9, x1, #63
+; CHECK-GI-NEXT:    asr x10, x0, #63
+; CHECK-GI-NEXT:    mul x8, x0, x1
+; CHECK-GI-NEXT:    mul x9, x0, x9
+; CHECK-GI-NEXT:    umulh x11, x0, x1
+; CHECK-GI-NEXT:    mov x0, x8
+; CHECK-GI-NEXT:    madd x9, x10, x1, x9
+; CHECK-GI-NEXT:    add x1, x9, x11
+; CHECK-GI-NEXT:    ret
 entry:
   %tmp1 = sext i64 %a to i128
   %tmp2 = sext i64 %b to i128
@@ -139,12 +152,20 @@ entry:
 
 ; Check the sext_inreg case.
 define i64 @t11(i64 %a) nounwind {
-; CHECK-LABEL: t11:
-; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov w8, #29594 // =0x739a
-; CHECK-NEXT:    movk w8, #65499, lsl #16
-; CHECK-NEXT:    smnegl x0, w0, w8
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: t11:
+; CHECK-SD:       // %bb.0: // %entry
+; CHECK-SD-NEXT:    mov w8, #29594 // =0x739a
+; CHECK-SD-NEXT:    movk w8, #65499, lsl #16
+; CHECK-SD-NEXT:    smnegl x0, w0, w8
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: t11:
+; CHECK-GI:       // %bb.0: // %entry
+; CHECK-GI-NEXT:    sxtw x8, w0
+; CHECK-GI-NEXT:    mov x9, #-35942 // =0xffffffffffff739a
+; CHECK-GI-NEXT:    movk x9, #65499, lsl #16
+; CHECK-GI-NEXT:    mneg x0, x8, x9
+; CHECK-GI-NEXT:    ret
 entry:
   %tmp1 = trunc i64 %a to i32
   %tmp2 = sext i32 %tmp1 to i64
@@ -154,12 +175,20 @@ entry:
 }
 
 define i64 @t12(i64 %a, i64 %b) nounwind {
-; CHECK-LABEL: t12:
-; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov w8, #35118 // =0x892e
-; CHECK-NEXT:    movk w8, #65008, lsl #16
-; CHECK-NEXT:    smaddl x0, w0, w8, x1
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: t12:
+; CHECK-SD:       // %bb.0: // %entry
+; CHECK-SD-NEXT:    mov w8, #35118 // =0x892e
+; CHECK-SD-NEXT:    movk w8, #65008, lsl #16
+; CHECK-SD-NEXT:    smaddl x0, w0, w8, x1
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: t12:
+; CHECK-GI:       // %bb.0: // %entry
+; CHECK-GI-NEXT:    sxtw x8, w0
+; CHECK-GI-NEXT:    mov x9, #-30418 // =0xffffffffffff892e
+; CHECK-GI-NEXT:    movk x9, #65008, lsl #16
+; CHECK-GI-NEXT:    madd x0, x8, x9, x1
+; CHECK-GI-NEXT:    ret
 entry:
   %tmp1 = trunc i64 %a to i32
   %tmp2 = sext i32 %tmp1 to i64