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[LV] Add missing test cover for replicating load/store costs.
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‎llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs.ll‎

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --filter-out-after "scalar.ph:" --version 6
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; RUN: opt -p loop-vectorize -S %s | FileCheck %s
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target triple = "arm64-apple-macosx15.0.0"
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define void @replicating_load_used_as_store_addr(ptr noalias %A) {
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; CHECK-LABEL: define void @replicating_load_used_as_store_addr(
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; CHECK-SAME: ptr noalias [[A:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
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; CHECK: [[VECTOR_PH]]:
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; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
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; CHECK: [[VECTOR_BODY]]:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 1
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; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1
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; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP0]], 1
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; CHECK-NEXT: [[TMP3:%.*]] = getelementptr ptr, ptr [[A]], i64 [[INDEX]]
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; CHECK-NEXT: [[TMP4:%.*]] = getelementptr ptr, ptr [[A]], i64 [[TMP0]]
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; CHECK-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP3]], align 8
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; CHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP4]], align 8
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; CHECK-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP1]] to i32
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; CHECK-NEXT: [[TMP8:%.*]] = trunc i64 [[TMP2]] to i32
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; CHECK-NEXT: store i32 [[TMP7]], ptr [[TMP5]], align 4
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; CHECK-NEXT: store i32 [[TMP8]], ptr [[TMP6]], align 4
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
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; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100
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; CHECK-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK: [[MIDDLE_BLOCK]]:
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; CHECK-NEXT: br label %[[SCALAR_PH:.*]]
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; CHECK: [[SCALAR_PH]]:
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;
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entry:
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br label %loop
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loop:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
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%iv.next = add i64 %iv, 1
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%gep.A = getelementptr ptr, ptr %A, i64 %iv
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%l.p = load ptr, ptr %gep.A, align 8
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%iv.trunc = trunc i64 %iv.next to i32
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store i32 %iv.trunc, ptr %l.p, align 4
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%ec = icmp eq i64 %iv, 100
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br i1 %ec, label %exit, label %loop
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exit:
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ret void
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}
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define void @replicating_load_used_as_store_addr_2(ptr noalias %invar.dst, ptr noalias %invar.src, ptr noalias %src) {
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; CHECK-LABEL: define void @replicating_load_used_as_store_addr_2(
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; CHECK-SAME: ptr noalias [[INVAR_DST:%.*]], ptr noalias [[INVAR_SRC:%.*]], ptr noalias [[SRC:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
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; CHECK: [[VECTOR_PH]]:
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; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
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; CHECK: [[VECTOR_BODY]]:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[INVAR_SRC]], align 4
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; CHECK-NEXT: [[TMP1:%.*]] = sext i32 [[TMP0]] to i64
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; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i128, ptr [[SRC]], i64 [[TMP1]]
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; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
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; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[TMP3]], 123
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; CHECK-NEXT: store i32 [[TMP4]], ptr [[INVAR_DST]], align 8
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
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; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100
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; CHECK-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
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; CHECK: [[MIDDLE_BLOCK]]:
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; CHECK-NEXT: br [[EXIT:label %.*]]
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; CHECK: [[SCALAR_PH:.*:]]
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;
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entry:
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br label %loop
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loop:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
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%l.offset = load i32, ptr %invar.src, align 4
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%offset.ext = sext i32 %l.offset to i64
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%gep.src = getelementptr i128, ptr %src, i64 %offset.ext
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%l.v = load i32, ptr %gep.src, align 4
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%add = add i32 %l.v, 123
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store i32 %add, ptr %invar.dst, align 8
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%iv.next = add i64 %iv, 1
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%exitcond41.not = icmp eq i64 %iv.next, 100
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br i1 %exitcond41.not, label %exit, label %loop
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exit:
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ret void
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}
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define void @replicating_load_used_as_store_addr_3(ptr noalias %src, ptr noalias %dst, ptr noalias %invar.dst, i8 %x) {
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; CHECK-LABEL: define void @replicating_load_used_as_store_addr_3(
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; CHECK-SAME: ptr noalias [[SRC:%.*]], ptr noalias [[DST:%.*]], ptr noalias [[INVAR_DST:%.*]], i8 [[X:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
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; CHECK: [[VECTOR_PH]]:
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; CHECK-NEXT: [[TMP0:%.*]] = xor i8 [[X]], 10
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; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[TMP0]] to i64
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; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP1]]
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; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
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; CHECK: [[VECTOR_BODY]]:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr [[TMP2]], align 1
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; CHECK-NEXT: [[TMP4:%.*]] = zext i8 [[TMP3]] to i32
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; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP4]], 111
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; CHECK-NEXT: [[TMP6:%.*]] = zext i32 [[TMP4]] to i64
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; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP6]]
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; CHECK-NEXT: store i8 0, ptr [[TMP7]], align 1
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; CHECK-NEXT: store i8 0, ptr [[TMP7]], align 1
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; CHECK-NEXT: [[TMP8:%.*]] = trunc i32 [[TMP5]] to i8
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; CHECK-NEXT: store i8 [[TMP8]], ptr [[INVAR_DST]], align 1
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
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; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100
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; CHECK-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
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; CHECK: [[MIDDLE_BLOCK]]:
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; CHECK-NEXT: br [[EXIT:label %.*]]
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; CHECK: [[SCALAR_PH:.*:]]
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;
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entry:
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br label %loop
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loop:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
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%xor = xor i8 %x, 10
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%ext = zext i8 %xor to i64
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%gep.src = getelementptr i8, ptr %src, i64 %ext
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%l = load i8, ptr %gep.src, align 1
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%l.ext = zext i8 %l to i32
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%xor.2 = xor i32 %l.ext, 111
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%idx2.ext = zext i32 %l.ext to i64
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%gep.dst = getelementptr i8, ptr %dst, i64 %idx2.ext
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store i8 0, ptr %gep.dst, align 1
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%xor.2.trunc = trunc i32 %xor.2 to i8
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store i8 %xor.2.trunc, ptr %invar.dst, align 1
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%iv.next = add i64 %iv, 1
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%ec = icmp eq i64 %iv.next, 100
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br i1 %ec, label %exit, label %loop
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exit:
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ret void
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}
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define void @uniform_gep_for_replicating_gep(ptr %dst) {
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; CHECK-LABEL: define void @uniform_gep_for_replicating_gep(
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; CHECK-SAME: ptr [[DST:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
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; CHECK: [[VECTOR_PH]]:
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; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
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; CHECK: [[VECTOR_BODY]]:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[VEC_IND:%.*]] = phi <2 x i32> [ <i32 0, i32 1>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[STEP_ADD:%.*]] = add <2 x i32> [[VEC_IND]], splat (i32 2)
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; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[INDEX]], 0
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; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[INDEX]], 1
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; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[INDEX]], 2
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; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[INDEX]], 3
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; CHECK-NEXT: [[TMP4:%.*]] = icmp eq <2 x i32> [[VEC_IND]], zeroinitializer
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; CHECK-NEXT: [[TMP5:%.*]] = icmp eq <2 x i32> [[STEP_ADD]], zeroinitializer
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; CHECK-NEXT: [[TMP6:%.*]] = lshr i32 [[TMP0]], 1
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; CHECK-NEXT: [[TMP7:%.*]] = lshr i32 [[TMP1]], 1
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; CHECK-NEXT: [[TMP8:%.*]] = lshr i32 [[TMP2]], 1
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; CHECK-NEXT: [[TMP9:%.*]] = lshr i32 [[TMP3]], 1
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; CHECK-NEXT: [[TMP10:%.*]] = zext <2 x i1> [[TMP4]] to <2 x i8>
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; CHECK-NEXT: [[TMP11:%.*]] = zext <2 x i1> [[TMP5]] to <2 x i8>
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; CHECK-NEXT: [[TMP12:%.*]] = zext i32 [[TMP6]] to i64
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; CHECK-NEXT: [[TMP13:%.*]] = zext i32 [[TMP7]] to i64
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; CHECK-NEXT: [[TMP14:%.*]] = zext i32 [[TMP8]] to i64
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; CHECK-NEXT: [[TMP15:%.*]] = zext i32 [[TMP9]] to i64
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; CHECK-NEXT: [[TMP16:%.*]] = getelementptr i64, ptr [[DST]], i64 [[TMP12]]
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; CHECK-NEXT: [[TMP17:%.*]] = getelementptr i64, ptr [[DST]], i64 [[TMP13]]
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; CHECK-NEXT: [[TMP18:%.*]] = getelementptr i64, ptr [[DST]], i64 [[TMP14]]
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; CHECK-NEXT: [[TMP19:%.*]] = getelementptr i64, ptr [[DST]], i64 [[TMP15]]
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; CHECK-NEXT: [[TMP20:%.*]] = extractelement <2 x i8> [[TMP10]], i32 0
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; CHECK-NEXT: store i8 [[TMP20]], ptr [[TMP16]], align 1
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; CHECK-NEXT: [[TMP21:%.*]] = extractelement <2 x i8> [[TMP10]], i32 1
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; CHECK-NEXT: store i8 [[TMP21]], ptr [[TMP17]], align 1
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; CHECK-NEXT: [[TMP22:%.*]] = extractelement <2 x i8> [[TMP11]], i32 0
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; CHECK-NEXT: store i8 [[TMP22]], ptr [[TMP18]], align 1
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; CHECK-NEXT: [[TMP23:%.*]] = extractelement <2 x i8> [[TMP11]], i32 1
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; CHECK-NEXT: store i8 [[TMP23]], ptr [[TMP19]], align 1
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
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; CHECK-NEXT: [[VEC_IND_NEXT]] = add <2 x i32> [[STEP_ADD]], splat (i32 2)
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; CHECK-NEXT: [[TMP24:%.*]] = icmp eq i32 [[INDEX_NEXT]], 128
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; CHECK-NEXT: br i1 [[TMP24]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
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; CHECK: [[MIDDLE_BLOCK]]:
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; CHECK-NEXT: br label %[[SCALAR_PH:.*]]
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; CHECK: [[SCALAR_PH]]:
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;
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entry:
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br label %loop
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loop:
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%iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ]
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%c = icmp eq i32 %iv, 0
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%shift = lshr i32 %iv, 1
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%ext = zext i1 %c to i8
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%ext.shift = zext i32 %shift to i64
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%gep = getelementptr i64, ptr %dst, i64 %ext.shift
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store i8 %ext, ptr %gep, align 1
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%iv.next = add i32 %iv, 1
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%ec = icmp eq i32 %iv, 128
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br i1 %ec, label %exit, label %loop
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exit:
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ret void
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}
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define void @test_load_gep_widen_induction(ptr noalias %dst, ptr noalias %dst2) #0 {
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; CHECK-LABEL: define void @test_load_gep_widen_induction(
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; CHECK-SAME: ptr noalias [[DST:%.*]], ptr noalias [[DST2:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
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; CHECK: [[VECTOR_PH]]:
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; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
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; CHECK: [[VECTOR_BODY]]:
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; CHECK-NEXT: [[OFFSET_IDX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[VEC_IND:%.*]] = phi <2 x i64> [ <i64 0, i64 1>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[STEP_ADD:%.*]] = add <2 x i64> [[VEC_IND]], splat (i64 2)
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; CHECK-NEXT: [[STEP_ADD_2:%.*]] = add <2 x i64> [[STEP_ADD]], splat (i64 2)
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; CHECK-NEXT: [[STEP_ADD_3:%.*]] = add <2 x i64> [[STEP_ADD_2]], splat (i64 2)
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; CHECK-NEXT: [[TMP0:%.*]] = getelementptr i128, ptr [[DST]], <2 x i64> [[VEC_IND]]
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; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i128, ptr [[DST]], <2 x i64> [[STEP_ADD]]
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; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i128, ptr [[DST]], <2 x i64> [[STEP_ADD_2]]
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; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i128, ptr [[DST]], <2 x i64> [[STEP_ADD_3]]
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; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x ptr> [[TMP0]], i32 0
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; CHECK-NEXT: store ptr null, ptr [[TMP4]], align 8
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; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x ptr> [[TMP0]], i32 1
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; CHECK-NEXT: store ptr null, ptr [[TMP5]], align 8
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; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x ptr> [[TMP1]], i32 0
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; CHECK-NEXT: store ptr null, ptr [[TMP6]], align 8
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; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x ptr> [[TMP1]], i32 1
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; CHECK-NEXT: store ptr null, ptr [[TMP7]], align 8
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; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x ptr> [[TMP2]], i32 0
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; CHECK-NEXT: store ptr null, ptr [[TMP8]], align 8
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; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x ptr> [[TMP2]], i32 1
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; CHECK-NEXT: store ptr null, ptr [[TMP9]], align 8
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; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x ptr> [[TMP3]], i32 0
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; CHECK-NEXT: store ptr null, ptr [[TMP10]], align 8
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; CHECK-NEXT: [[TMP11:%.*]] = extractelement <2 x ptr> [[TMP3]], i32 1
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; CHECK-NEXT: store ptr null, ptr [[TMP11]], align 8
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; CHECK-NEXT: [[TMP12:%.*]] = getelementptr ptr, ptr [[DST2]], i64 [[OFFSET_IDX]]
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; CHECK-NEXT: [[TMP13:%.*]] = getelementptr ptr, ptr [[TMP12]], i32 2
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; CHECK-NEXT: [[TMP14:%.*]] = getelementptr ptr, ptr [[TMP12]], i32 4
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; CHECK-NEXT: [[TMP15:%.*]] = getelementptr ptr, ptr [[TMP12]], i32 6
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; CHECK-NEXT: store <2 x ptr> [[TMP0]], ptr [[TMP12]], align 8
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; CHECK-NEXT: store <2 x ptr> [[TMP1]], ptr [[TMP13]], align 8
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; CHECK-NEXT: store <2 x ptr> [[TMP2]], ptr [[TMP14]], align 8
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; CHECK-NEXT: store <2 x ptr> [[TMP3]], ptr [[TMP15]], align 8
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[OFFSET_IDX]], 8
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; CHECK-NEXT: [[VEC_IND_NEXT]] = add <2 x i64> [[STEP_ADD_3]], splat (i64 2)
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; CHECK-NEXT: [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT]], 96
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; CHECK-NEXT: br i1 [[TMP16]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
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; CHECK: [[MIDDLE_BLOCK]]:
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; CHECK-NEXT: br label %[[SCALAR_PH:.*]]
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; CHECK: [[SCALAR_PH]]:
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;
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entry:
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br label %loop
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loop: ; preds = %loop, %entry
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
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%gep.dst.iv = getelementptr i128, ptr %dst, i64 %iv
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%iv.next = add i64 %iv, 1
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store ptr null, ptr %gep.dst.iv, align 8
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%gep.dst2.iv = getelementptr ptr, ptr %dst2, i64 %iv
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store ptr %gep.dst.iv, ptr %gep.dst2.iv
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%exitcond.not = icmp eq i64 %iv.next, 100
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br i1 %exitcond.not, label %exit, label %loop
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exit:
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ret void
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}
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define ptr @replicating_store_in_conditional_latch(ptr %p, i32 %n) #0 {
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; CHECK-LABEL: define ptr @replicating_store_in_conditional_latch(
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; CHECK-SAME: ptr [[P:%.*]], i32 [[N:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: [[TMP0:%.*]] = sub i32 0, [[N]]
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; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
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; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 1
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; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
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; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ule i64 [[TMP3]], 4
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; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
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; CHECK: [[VECTOR_PH]]:
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; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP3]], 4
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; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[N_MOD_VF]], 0
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; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 4, i64 [[N_MOD_VF]]
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; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP3]], [[TMP5]]
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; CHECK-NEXT: [[DOTCAST:%.*]] = trunc i64 [[N_VEC]] to i32
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; CHECK-NEXT: [[TMP6:%.*]] = mul i32 [[DOTCAST]], -2
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; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[N_VEC]], 48
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; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP7]]
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; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
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; CHECK: [[VECTOR_BODY]]:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 48
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; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[OFFSET_IDX]], 48
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; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[OFFSET_IDX]], 96
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; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[OFFSET_IDX]], 144
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; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[P]], i64 [[OFFSET_IDX]]
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; CHECK-NEXT: [[NEXT_GEP1:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP9]]
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; CHECK-NEXT: [[NEXT_GEP2:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP10]]
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; CHECK-NEXT: [[NEXT_GEP3:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP11]]
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; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[NEXT_GEP]], i64 24
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; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i8, ptr [[NEXT_GEP1]], i64 24
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; CHECK-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[NEXT_GEP2]], i64 24
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; CHECK-NEXT: [[TMP15:%.*]] = getelementptr i8, ptr [[NEXT_GEP3]], i64 24
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; CHECK-NEXT: store ptr null, ptr [[TMP12]], align 8
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; CHECK-NEXT: store ptr null, ptr [[TMP13]], align 8
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; CHECK-NEXT: store ptr null, ptr [[TMP14]], align 8
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; CHECK-NEXT: store ptr null, ptr [[TMP15]], align 8
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
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; CHECK-NEXT: [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[TMP16]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]
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; CHECK: [[MIDDLE_BLOCK]]:
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; CHECK-NEXT: br label %[[SCALAR_PH]]
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; CHECK: [[SCALAR_PH]]:
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;
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entry:
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br label %loop.header
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loop.header:
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%iv = phi i32 [ 0, %entry ], [ %iv.next, %loop.latch ]
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%ptr.iv = phi ptr [ %p, %entry ], [ %ptr.iv.next, %loop.latch ]
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%gep.ptr.iv = getelementptr i8, ptr %ptr.iv, i64 24
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%c = icmp eq i32 %iv, %n
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br i1 %c, label %exit, label %loop.latch
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loop.latch:
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%iv.next = add nsw i32 %iv, -2
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store ptr null, ptr %gep.ptr.iv, align 8
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%ptr.iv.next = getelementptr i8, ptr %ptr.iv, i64 48
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br label %loop.header
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exit:
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ret ptr %gep.ptr.iv
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}
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attributes #0 = { "target-cpu"="neoverse-512tvb" }

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