Skip to content

Commit 70a825c

Browse files
AZero13AZero13
committed
Remove CSEL a, b, cc, SUBS(SUB(x,y), 0) -> CSEL a, b, cc, SUBS(x,y)
This should be done in peephole, not in DAG.
1 parent 0fa3061 commit 70a825c

File tree

8 files changed

+228
-323
lines changed

8 files changed

+228
-323
lines changed

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp‎

Lines changed: 0 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -25815,29 +25815,6 @@ static SDValue performCSELCombine(SDNode *N,
2581525815
}
2581625816
}
2581725817

25818-
// CSEL a, b, cc, SUBS(SUB(x,y), 0) -> CSEL a, b, cc, SUBS(x,y) if cc doesn't
25819-
// use overflow flags, to avoid the comparison with zero. In case of success,
25820-
// this also replaces the original SUB(x,y) with the newly created SUBS(x,y).
25821-
// NOTE: Perhaps in the future use performFlagSettingCombine to replace SUB
25822-
// nodes with their SUBS equivalent as is already done for other flag-setting
25823-
// operators, in which case doing the replacement here becomes redundant.
25824-
if (Cond.getOpcode() == AArch64ISD::SUBS && Cond->hasNUsesOfValue(1, 1) &&
25825-
isNullConstant(Cond.getOperand(1))) {
25826-
SDValue Sub = Cond.getOperand(0);
25827-
AArch64CC::CondCode CC =
25828-
static_cast<AArch64CC::CondCode>(N->getConstantOperandVal(2));
25829-
if (Sub.getOpcode() == ISD::SUB &&
25830-
(CC == AArch64CC::EQ || CC == AArch64CC::NE || CC == AArch64CC::MI ||
25831-
CC == AArch64CC::PL)) {
25832-
SDLoc DL(N);
25833-
SDValue Subs = DAG.getNode(AArch64ISD::SUBS, DL, Cond->getVTList(),
25834-
Sub.getOperand(0), Sub.getOperand(1));
25835-
DCI.CombineTo(Sub.getNode(), Subs);
25836-
DCI.CombineTo(Cond.getNode(), Subs, Subs.getValue(1));
25837-
return SDValue(N, 0);
25838-
}
25839-
}
25840-
2584125818
// CSEL (LASTB P, Z), X, NE(ANY P) -> CLASTB P, X, Z
2584225819
if (SDValue CondLast = foldCSELofLASTB(N, DAG))
2584325820
return CondLast;

‎llvm/test/CodeGen/AArch64/abds-neg.ll‎

Lines changed: 10 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,8 @@ define i8 @abd_ext_i8(i8 %a, i8 %b) nounwind {
99
; CHECK-LABEL: abd_ext_i8:
1010
; CHECK: // %bb.0:
1111
; CHECK-NEXT: sxtb w8, w0
12-
; CHECK-NEXT: subs w8, w8, w1, sxtb
12+
; CHECK-NEXT: sub w8, w8, w1, sxtb
13+
; CHECK-NEXT: cmp w8, #0
1314
; CHECK-NEXT: cneg w0, w8, pl
1415
; CHECK-NEXT: ret
1516
%aext = sext i8 %a to i64
@@ -25,7 +26,8 @@ define i8 @abd_ext_i8_i16(i8 %a, i16 %b) nounwind {
2526
; CHECK-LABEL: abd_ext_i8_i16:
2627
; CHECK: // %bb.0:
2728
; CHECK-NEXT: sxtb w8, w0
28-
; CHECK-NEXT: subs w8, w8, w1, sxth
29+
; CHECK-NEXT: sub w8, w8, w1, sxth
30+
; CHECK-NEXT: cmp w8, #0
2931
; CHECK-NEXT: cneg w0, w8, pl
3032
; CHECK-NEXT: ret
3133
%aext = sext i8 %a to i64
@@ -41,7 +43,8 @@ define i8 @abd_ext_i8_undef(i8 %a, i8 %b) nounwind {
4143
; CHECK-LABEL: abd_ext_i8_undef:
4244
; CHECK: // %bb.0:
4345
; CHECK-NEXT: sxtb w8, w0
44-
; CHECK-NEXT: subs w8, w8, w1, sxtb
46+
; CHECK-NEXT: sub w8, w8, w1, sxtb
47+
; CHECK-NEXT: cmp w8, #0
4548
; CHECK-NEXT: cneg w0, w8, pl
4649
; CHECK-NEXT: ret
4750
%aext = sext i8 %a to i64
@@ -57,7 +60,8 @@ define i16 @abd_ext_i16(i16 %a, i16 %b) nounwind {
5760
; CHECK-LABEL: abd_ext_i16:
5861
; CHECK: // %bb.0:
5962
; CHECK-NEXT: sxth w8, w0
60-
; CHECK-NEXT: subs w8, w8, w1, sxth
63+
; CHECK-NEXT: sub w8, w8, w1, sxth
64+
; CHECK-NEXT: cmp w8, #0
6165
; CHECK-NEXT: cneg w0, w8, pl
6266
; CHECK-NEXT: ret
6367
%aext = sext i16 %a to i64
@@ -89,7 +93,8 @@ define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {
8993
; CHECK-LABEL: abd_ext_i16_undef:
9094
; CHECK: // %bb.0:
9195
; CHECK-NEXT: sxth w8, w0
92-
; CHECK-NEXT: subs w8, w8, w1, sxth
96+
; CHECK-NEXT: sub w8, w8, w1, sxth
97+
; CHECK-NEXT: cmp w8, #0
9398
; CHECK-NEXT: cneg w0, w8, pl
9499
; CHECK-NEXT: ret
95100
%aext = sext i16 %a to i64

‎llvm/test/CodeGen/AArch64/abds.ll‎

Lines changed: 28 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,8 @@ define i8 @abd_ext_i8(i8 %a, i8 %b) nounwind {
99
; CHECK-LABEL: abd_ext_i8:
1010
; CHECK: // %bb.0:
1111
; CHECK-NEXT: sxtb w8, w0
12-
; CHECK-NEXT: subs w8, w8, w1, sxtb
12+
; CHECK-NEXT: sub w8, w8, w1, sxtb
13+
; CHECK-NEXT: cmp w8, #0
1314
; CHECK-NEXT: cneg w0, w8, mi
1415
; CHECK-NEXT: ret
1516
%aext = sext i8 %a to i64
@@ -24,7 +25,8 @@ define i8 @abd_ext_i8_i16(i8 %a, i16 %b) nounwind {
2425
; CHECK-LABEL: abd_ext_i8_i16:
2526
; CHECK: // %bb.0:
2627
; CHECK-NEXT: sxtb w8, w0
27-
; CHECK-NEXT: subs w8, w8, w1, sxth
28+
; CHECK-NEXT: sub w8, w8, w1, sxth
29+
; CHECK-NEXT: cmp w8, #0
2830
; CHECK-NEXT: cneg w0, w8, mi
2931
; CHECK-NEXT: ret
3032
%aext = sext i8 %a to i64
@@ -39,7 +41,8 @@ define i8 @abd_ext_i8_undef(i8 %a, i8 %b) nounwind {
3941
; CHECK-LABEL: abd_ext_i8_undef:
4042
; CHECK: // %bb.0:
4143
; CHECK-NEXT: sxtb w8, w0
42-
; CHECK-NEXT: subs w8, w8, w1, sxtb
44+
; CHECK-NEXT: sub w8, w8, w1, sxtb
45+
; CHECK-NEXT: cmp w8, #0
4346
; CHECK-NEXT: cneg w0, w8, mi
4447
; CHECK-NEXT: ret
4548
%aext = sext i8 %a to i64
@@ -54,7 +57,8 @@ define i16 @abd_ext_i16(i16 %a, i16 %b) nounwind {
5457
; CHECK-LABEL: abd_ext_i16:
5558
; CHECK: // %bb.0:
5659
; CHECK-NEXT: sxth w8, w0
57-
; CHECK-NEXT: subs w8, w8, w1, sxth
60+
; CHECK-NEXT: sub w8, w8, w1, sxth
61+
; CHECK-NEXT: cmp w8, #0
5862
; CHECK-NEXT: cneg w0, w8, mi
5963
; CHECK-NEXT: ret
6064
%aext = sext i16 %a to i64
@@ -84,7 +88,8 @@ define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {
8488
; CHECK-LABEL: abd_ext_i16_undef:
8589
; CHECK: // %bb.0:
8690
; CHECK-NEXT: sxth w8, w0
87-
; CHECK-NEXT: subs w8, w8, w1, sxth
91+
; CHECK-NEXT: sub w8, w8, w1, sxth
92+
; CHECK-NEXT: cmp w8, #0
8893
; CHECK-NEXT: cneg w0, w8, mi
8994
; CHECK-NEXT: ret
9095
%aext = sext i16 %a to i64
@@ -209,7 +214,8 @@ define i8 @abd_minmax_i8(i8 %a, i8 %b) nounwind {
209214
; CHECK-LABEL: abd_minmax_i8:
210215
; CHECK: // %bb.0:
211216
; CHECK-NEXT: sxtb w8, w0
212-
; CHECK-NEXT: subs w8, w8, w1, sxtb
217+
; CHECK-NEXT: sub w8, w8, w1, sxtb
218+
; CHECK-NEXT: cmp w8, #0
213219
; CHECK-NEXT: cneg w0, w8, mi
214220
; CHECK-NEXT: ret
215221
%min = call i8 @llvm.smin.i8(i8 %a, i8 %b)
@@ -222,7 +228,8 @@ define i16 @abd_minmax_i16(i16 %a, i16 %b) nounwind {
222228
; CHECK-LABEL: abd_minmax_i16:
223229
; CHECK: // %bb.0:
224230
; CHECK-NEXT: sxth w8, w0
225-
; CHECK-NEXT: subs w8, w8, w1, sxth
231+
; CHECK-NEXT: sub w8, w8, w1, sxth
232+
; CHECK-NEXT: cmp w8, #0
226233
; CHECK-NEXT: cneg w0, w8, mi
227234
; CHECK-NEXT: ret
228235
%min = call i16 @llvm.smin.i16(i16 %a, i16 %b)
@@ -279,7 +286,8 @@ define i8 @abd_cmp_i8(i8 %a, i8 %b) nounwind {
279286
; CHECK-LABEL: abd_cmp_i8:
280287
; CHECK: // %bb.0:
281288
; CHECK-NEXT: sxtb w8, w0
282-
; CHECK-NEXT: subs w8, w8, w1, sxtb
289+
; CHECK-NEXT: sub w8, w8, w1, sxtb
290+
; CHECK-NEXT: cmp w8, #0
283291
; CHECK-NEXT: cneg w0, w8, mi
284292
; CHECK-NEXT: ret
285293
%cmp = icmp sgt i8 %a, %b
@@ -293,7 +301,8 @@ define i16 @abd_cmp_i16(i16 %a, i16 %b) nounwind {
293301
; CHECK-LABEL: abd_cmp_i16:
294302
; CHECK: // %bb.0:
295303
; CHECK-NEXT: sxth w8, w0
296-
; CHECK-NEXT: subs w8, w8, w1, sxth
304+
; CHECK-NEXT: sub w8, w8, w1, sxth
305+
; CHECK-NEXT: cmp w8, #0
297306
; CHECK-NEXT: cneg w0, w8, mi
298307
; CHECK-NEXT: ret
299308
%cmp = icmp sge i16 %a, %b
@@ -497,8 +506,12 @@ define i64 @vector_legalized(i16 %a, i16 %b) {
497506
; CHECK-LABEL: vector_legalized:
498507
; CHECK: // %bb.0:
499508
; CHECK-NEXT: sxth w8, w0
500-
; CHECK-NEXT: subs w8, w8, w1, sxth
501-
; CHECK-NEXT: cneg w0, w8, mi
509+
; CHECK-NEXT: sub w8, w8, w1, sxth
510+
; CHECK-NEXT: addp d0, v0.2d
511+
; CHECK-NEXT: cmp w8, #0
512+
; CHECK-NEXT: cneg w8, w8, mi
513+
; CHECK-NEXT: fmov x9, d0
514+
; CHECK-NEXT: add x0, x9, x8
502515
; CHECK-NEXT: ret
503516
%ea = sext i16 %a to i32
504517
%eb = sext i16 %b to i32
@@ -518,7 +531,8 @@ define i8 @abd_select_i8(i8 %a, i8 %b) nounwind {
518531
; CHECK-LABEL: abd_select_i8:
519532
; CHECK: // %bb.0:
520533
; CHECK-NEXT: sxtb w8, w0
521-
; CHECK-NEXT: subs w8, w8, w1, sxtb
534+
; CHECK-NEXT: sub w8, w8, w1, sxtb
535+
; CHECK-NEXT: cmp w8, #0
522536
; CHECK-NEXT: cneg w0, w8, mi
523537
; CHECK-NEXT: ret
524538
%cmp = icmp slt i8 %a, %b
@@ -532,7 +546,8 @@ define i16 @abd_select_i16(i16 %a, i16 %b) nounwind {
532546
; CHECK-LABEL: abd_select_i16:
533547
; CHECK: // %bb.0:
534548
; CHECK-NEXT: sxth w8, w0
535-
; CHECK-NEXT: subs w8, w8, w1, sxth
549+
; CHECK-NEXT: sub w8, w8, w1, sxth
550+
; CHECK-NEXT: cmp w8, #0
536551
; CHECK-NEXT: cneg w0, w8, mi
537552
; CHECK-NEXT: ret
538553
%cmp = icmp sle i16 %a, %b

‎llvm/test/CodeGen/AArch64/abdu-neg.ll‎

Lines changed: 10 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,8 @@ define i8 @abd_ext_i8(i8 %a, i8 %b) nounwind {
99
; CHECK-LABEL: abd_ext_i8:
1010
; CHECK: // %bb.0:
1111
; CHECK-NEXT: and w8, w0, #0xff
12-
; CHECK-NEXT: subs w8, w8, w1, uxtb
12+
; CHECK-NEXT: sub w8, w8, w1, uxtb
13+
; CHECK-NEXT: cmp w8, #0
1314
; CHECK-NEXT: cneg w0, w8, pl
1415
; CHECK-NEXT: ret
1516
%aext = zext i8 %a to i64
@@ -25,7 +26,8 @@ define i8 @abd_ext_i8_i16(i8 %a, i16 %b) nounwind {
2526
; CHECK-LABEL: abd_ext_i8_i16:
2627
; CHECK: // %bb.0:
2728
; CHECK-NEXT: and w8, w0, #0xff
28-
; CHECK-NEXT: subs w8, w8, w1, uxth
29+
; CHECK-NEXT: sub w8, w8, w1, uxth
30+
; CHECK-NEXT: cmp w8, #0
2931
; CHECK-NEXT: cneg w0, w8, pl
3032
; CHECK-NEXT: ret
3133
%aext = zext i8 %a to i64
@@ -41,7 +43,8 @@ define i8 @abd_ext_i8_undef(i8 %a, i8 %b) nounwind {
4143
; CHECK-LABEL: abd_ext_i8_undef:
4244
; CHECK: // %bb.0:
4345
; CHECK-NEXT: and w8, w0, #0xff
44-
; CHECK-NEXT: subs w8, w8, w1, uxtb
46+
; CHECK-NEXT: sub w8, w8, w1, uxtb
47+
; CHECK-NEXT: cmp w8, #0
4548
; CHECK-NEXT: cneg w0, w8, pl
4649
; CHECK-NEXT: ret
4750
%aext = zext i8 %a to i64
@@ -57,7 +60,8 @@ define i16 @abd_ext_i16(i16 %a, i16 %b) nounwind {
5760
; CHECK-LABEL: abd_ext_i16:
5861
; CHECK: // %bb.0:
5962
; CHECK-NEXT: and w8, w0, #0xffff
60-
; CHECK-NEXT: subs w8, w8, w1, uxth
63+
; CHECK-NEXT: sub w8, w8, w1, uxth
64+
; CHECK-NEXT: cmp w8, #0
6165
; CHECK-NEXT: cneg w0, w8, pl
6266
; CHECK-NEXT: ret
6367
%aext = zext i16 %a to i64
@@ -89,7 +93,8 @@ define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {
8993
; CHECK-LABEL: abd_ext_i16_undef:
9094
; CHECK: // %bb.0:
9195
; CHECK-NEXT: and w8, w0, #0xffff
92-
; CHECK-NEXT: subs w8, w8, w1, uxth
96+
; CHECK-NEXT: sub w8, w8, w1, uxth
97+
; CHECK-NEXT: cmp w8, #0
9398
; CHECK-NEXT: cneg w0, w8, pl
9499
; CHECK-NEXT: ret
95100
%aext = zext i16 %a to i64

‎llvm/test/CodeGen/AArch64/abdu.ll‎

Lines changed: 28 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,8 @@ define i8 @abd_ext_i8(i8 %a, i8 %b) nounwind {
99
; CHECK-LABEL: abd_ext_i8:
1010
; CHECK: // %bb.0:
1111
; CHECK-NEXT: and w8, w0, #0xff
12-
; CHECK-NEXT: subs w8, w8, w1, uxtb
12+
; CHECK-NEXT: sub w8, w8, w1, uxtb
13+
; CHECK-NEXT: cmp w8, #0
1314
; CHECK-NEXT: cneg w0, w8, mi
1415
; CHECK-NEXT: ret
1516
%aext = zext i8 %a to i64
@@ -24,7 +25,8 @@ define i8 @abd_ext_i8_i16(i8 %a, i16 %b) nounwind {
2425
; CHECK-LABEL: abd_ext_i8_i16:
2526
; CHECK: // %bb.0:
2627
; CHECK-NEXT: and w8, w0, #0xff
27-
; CHECK-NEXT: subs w8, w8, w1, uxth
28+
; CHECK-NEXT: sub w8, w8, w1, uxth
29+
; CHECK-NEXT: cmp w8, #0
2830
; CHECK-NEXT: cneg w0, w8, mi
2931
; CHECK-NEXT: ret
3032
%aext = zext i8 %a to i64
@@ -39,7 +41,8 @@ define i8 @abd_ext_i8_undef(i8 %a, i8 %b) nounwind {
3941
; CHECK-LABEL: abd_ext_i8_undef:
4042
; CHECK: // %bb.0:
4143
; CHECK-NEXT: and w8, w0, #0xff
42-
; CHECK-NEXT: subs w8, w8, w1, uxtb
44+
; CHECK-NEXT: sub w8, w8, w1, uxtb
45+
; CHECK-NEXT: cmp w8, #0
4346
; CHECK-NEXT: cneg w0, w8, mi
4447
; CHECK-NEXT: ret
4548
%aext = zext i8 %a to i64
@@ -54,7 +57,8 @@ define i16 @abd_ext_i16(i16 %a, i16 %b) nounwind {
5457
; CHECK-LABEL: abd_ext_i16:
5558
; CHECK: // %bb.0:
5659
; CHECK-NEXT: and w8, w0, #0xffff
57-
; CHECK-NEXT: subs w8, w8, w1, uxth
60+
; CHECK-NEXT: sub w8, w8, w1, uxth
61+
; CHECK-NEXT: cmp w8, #0
5862
; CHECK-NEXT: cneg w0, w8, mi
5963
; CHECK-NEXT: ret
6064
%aext = zext i16 %a to i64
@@ -84,7 +88,8 @@ define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {
8488
; CHECK-LABEL: abd_ext_i16_undef:
8589
; CHECK: // %bb.0:
8690
; CHECK-NEXT: and w8, w0, #0xffff
87-
; CHECK-NEXT: subs w8, w8, w1, uxth
91+
; CHECK-NEXT: sub w8, w8, w1, uxth
92+
; CHECK-NEXT: cmp w8, #0
8893
; CHECK-NEXT: cneg w0, w8, mi
8994
; CHECK-NEXT: ret
9095
%aext = zext i16 %a to i64
@@ -213,7 +218,8 @@ define i8 @abd_minmax_i8(i8 %a, i8 %b) nounwind {
213218
; CHECK-LABEL: abd_minmax_i8:
214219
; CHECK: // %bb.0:
215220
; CHECK-NEXT: and w8, w0, #0xff
216-
; CHECK-NEXT: subs w8, w8, w1, uxtb
221+
; CHECK-NEXT: sub w8, w8, w1, uxtb
222+
; CHECK-NEXT: cmp w8, #0
217223
; CHECK-NEXT: cneg w0, w8, mi
218224
; CHECK-NEXT: ret
219225
%min = call i8 @llvm.umin.i8(i8 %a, i8 %b)
@@ -226,7 +232,8 @@ define i16 @abd_minmax_i16(i16 %a, i16 %b) nounwind {
226232
; CHECK-LABEL: abd_minmax_i16:
227233
; CHECK: // %bb.0:
228234
; CHECK-NEXT: and w8, w0, #0xffff
229-
; CHECK-NEXT: subs w8, w8, w1, uxth
235+
; CHECK-NEXT: sub w8, w8, w1, uxth
236+
; CHECK-NEXT: cmp w8, #0
230237
; CHECK-NEXT: cneg w0, w8, mi
231238
; CHECK-NEXT: ret
232239
%min = call i16 @llvm.umin.i16(i16 %a, i16 %b)
@@ -285,7 +292,8 @@ define i8 @abd_cmp_i8(i8 %a, i8 %b) nounwind {
285292
; CHECK-LABEL: abd_cmp_i8:
286293
; CHECK: // %bb.0:
287294
; CHECK-NEXT: and w8, w0, #0xff
288-
; CHECK-NEXT: subs w8, w8, w1, uxtb
295+
; CHECK-NEXT: sub w8, w8, w1, uxtb
296+
; CHECK-NEXT: cmp w8, #0
289297
; CHECK-NEXT: cneg w0, w8, mi
290298
; CHECK-NEXT: ret
291299
%cmp = icmp ugt i8 %a, %b
@@ -299,7 +307,8 @@ define i16 @abd_cmp_i16(i16 %a, i16 %b) nounwind {
299307
; CHECK-LABEL: abd_cmp_i16:
300308
; CHECK: // %bb.0:
301309
; CHECK-NEXT: and w8, w0, #0xffff
302-
; CHECK-NEXT: subs w8, w8, w1, uxth
310+
; CHECK-NEXT: sub w8, w8, w1, uxth
311+
; CHECK-NEXT: cmp w8, #0
303312
; CHECK-NEXT: cneg w0, w8, mi
304313
; CHECK-NEXT: ret
305314
%cmp = icmp uge i16 %a, %b
@@ -362,8 +371,12 @@ define i64 @vector_legalized(i16 %a, i16 %b) {
362371
; CHECK-LABEL: vector_legalized:
363372
; CHECK: // %bb.0:
364373
; CHECK-NEXT: and w8, w0, #0xffff
365-
; CHECK-NEXT: subs w8, w8, w1, uxth
366-
; CHECK-NEXT: cneg w0, w8, mi
374+
; CHECK-NEXT: sub w8, w8, w1, uxth
375+
; CHECK-NEXT: cmp w8, #0
376+
; CHECK-NEXT: addp d0, v0.2d
377+
; CHECK-NEXT: cneg w8, w8, mi
378+
; CHECK-NEXT: fmov x9, d0
379+
; CHECK-NEXT: add x0, x9, x8
367380
; CHECK-NEXT: ret
368381
%ea = zext i16 %a to i32
369382
%eb = zext i16 %b to i32
@@ -383,7 +396,8 @@ define i8 @abd_select_i8(i8 %a, i8 %b) nounwind {
383396
; CHECK-LABEL: abd_select_i8:
384397
; CHECK: // %bb.0:
385398
; CHECK-NEXT: and w8, w0, #0xff
386-
; CHECK-NEXT: subs w8, w8, w1, uxtb
399+
; CHECK-NEXT: sub w8, w8, w1, uxtb
400+
; CHECK-NEXT: cmp w8, #0
387401
; CHECK-NEXT: cneg w0, w8, mi
388402
; CHECK-NEXT: ret
389403
%cmp = icmp ult i8 %a, %b
@@ -397,7 +411,8 @@ define i16 @abd_select_i16(i16 %a, i16 %b) nounwind {
397411
; CHECK-LABEL: abd_select_i16:
398412
; CHECK: // %bb.0:
399413
; CHECK-NEXT: and w8, w0, #0xffff
400-
; CHECK-NEXT: subs w8, w8, w1, uxth
414+
; CHECK-NEXT: sub w8, w8, w1, uxth
415+
; CHECK-NEXT: cmp w8, #0
401416
; CHECK-NEXT: cneg w0, w8, mi
402417
; CHECK-NEXT: ret
403418
%cmp = icmp ule i16 %a, %b

0 commit comments

Comments
 (0)