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hchandelhchandel
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Change Imm32 to SImm32
Change-Id: I1138c145571be288f566598214ebe183e1dfb99c
1 parent 09c3c2d commit 71206e8

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5 files changed

+27
-32
lines changed

5 files changed

+27
-32
lines changed

‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp‎

Lines changed: 4 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1056,18 +1056,13 @@ struct RISCVOperand final : public MCParsedAsmOperand {
10561056
isInt<26>(fixImmediateForRV32(Imm, isRV64Imm()));
10571057
}
10581058

1059-
bool isImm32() const {
1059+
bool isSImm32() const {
10601060
int64_t Imm;
10611061
RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
10621062
if (!isImm())
10631063
return false;
10641064
bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
1065-
bool IsValid;
1066-
if (!IsConstantImm)
1067-
IsValid = RISCVAsmParser::classifySymbolRef(getImm(), VK);
1068-
else
1069-
IsValid = isInt<32>(Imm) || isUInt<32>(Imm);
1070-
return IsValid && VK == RISCVMCExpr::VK_RISCV_None;
1065+
return IsConstantImm && isInt<32>(Imm) && VK == RISCVMCExpr::VK_RISCV_None;
10711066
}
10721067

10731068
/// getStartLoc - Gets location of the first token of this operand
@@ -1679,10 +1674,10 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
16791674
case Match_InvalidSImm26:
16801675
return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 25),
16811676
(1 << 25) - 1);
1682-
case Match_InvalidImm32:
1677+
case Match_InvalidSImm32:
16831678
return generateImmOutOfRangeError(Operands, ErrorInfo,
16841679
std::numeric_limits<int32_t>::min(),
1685-
std::numeric_limits<uint32_t>::max());
1680+
std::numeric_limits<int32_t>::max());
16861681
case Match_InvalidRnumArg: {
16871682
return generateImmOutOfRangeError(Operands, ErrorInfo, 0, 10);
16881683
}

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -326,7 +326,7 @@ enum OperandType : unsigned {
326326
OPERAND_SIMM12,
327327
OPERAND_SIMM12_LSB00000,
328328
OPERAND_SIMM26,
329-
OPERAND_IMM32,
329+
OPERAND_SIMM32,
330330
OPERAND_CLUI_IMM,
331331
OPERAND_VTYPEI10,
332332
OPERAND_VTYPEI11,

‎llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -36,16 +36,16 @@ def simm26 : RISCVSImmLeafOp<26>;
3636

3737
// 32-bit Immediate, used by RV32 Instructions in 32-bit operations, so no
3838
// sign-/zero-extension. This is represented internally as a signed 32-bit value.
39-
def imm32 : RISCVOp<XLenVT> {
40-
let ParserMatchClass = ImmAsmOperand<"", 32, "">;
39+
def simm32 : RISCVOp<XLenVT> {
40+
let ParserMatchClass = SImmAsmOperand<32, "">;
4141
let EncoderMethod = "getImmOpValue";
4242
let DecoderMethod = "decodeSImmOperand<32>";
43-
let OperandType = "OPERAND_IMM32";
43+
let OperandType = "OPERAND_SIMM32";
4444
let MCOperandPredicate = [{
4545
int64_t Imm;
4646
if (MCOp.evaluateAsConstantImm(Imm))
47-
return (isInt<32>(Imm));
48-
return MCOp.isBareSymbolRef();
47+
return isInt<32>(Imm);
48+
return false;
4949
}];
5050
}
5151

@@ -261,7 +261,7 @@ class QCIRVInstESStore<bits<3> funct3, bits<2> funct2, string opcodestr>
261261
opcodestr, "$rs2, ${imm}(${rs1})">;
262262

263263
class QCIRVInstEAI<bits<3> funct3, bits<1> funct1, string opcodestr>
264-
: RVInst48<(outs GPRNoX0:$rd_wb), (ins GPRNoX0:$rd, imm32:$imm),
264+
: RVInst48<(outs GPRNoX0:$rd_wb), (ins GPRNoX0:$rd, simm32:$imm),
265265
opcodestr, "$rd, $imm", [], InstFormatOther> {
266266
bits<5> rd;
267267
bits<32> imm;

‎llvm/test/MC/RISCV/xqcilia-invalid.s‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@ qc.e.addai 9, 33554432
1111
# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
1212
qc.e.addai x9
1313

14-
# CHECK-IMM: :[[@LINE+1]]:16: error: immediate must be an integer in the range [-2147483648, 4294967295]
14+
# CHECK-IMM: :[[@LINE+1]]:16: error: immediate must be an integer in the range [-2147483648, 2147483647]
1515
qc.e.addai x9, 20485546494
1616

1717
# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
@@ -39,7 +39,7 @@ qc.e.andai 9, 33554432
3939
# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
4040
qc.e.andai x9
4141

42-
# CHECK-IMM: :[[@LINE+1]]:16: error: immediate must be an integer in the range [-2147483648, 4294967295]
42+
# CHECK-IMM: :[[@LINE+1]]:16: error: immediate must be an integer in the range [-2147483648, 2147483647]
4343
qc.e.andai x9, 20494437494
4444

4545
# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
@@ -67,7 +67,7 @@ qc.e.orai 9, 33554432
6767
# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
6868
qc.e.orai x9
6969

70-
# CHECK-IMM: :[[@LINE+1]]:15: error: immediate must be an integer in the range [-2147483648, 4294967295]
70+
# CHECK-IMM: :[[@LINE+1]]:15: error: immediate must be an integer in the range [-2147483648, 2147483647]
7171
qc.e.orai x9, 20494437494
7272

7373
# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
@@ -96,7 +96,7 @@ qc.e.xorai 9, 33554432
9696
# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
9797
qc.e.xorai x9
9898

99-
# CHECK-IMM: :[[@LINE+1]]:16: error: immediate must be an integer in the range [-2147483648, 4294967295]
99+
# CHECK-IMM: :[[@LINE+1]]:16: error: immediate must be an integer in the range [-2147483648, 2147483647]
100100
qc.e.xorai x9, 20494437494
101101

102102
# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)

‎llvm/test/MC/RISCV/xqcilia-valid.s‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -10,9 +10,9 @@
1010
# RUN: | llvm-objdump --mattr=+experimental-xqcilia --no-print-imm-hex -d - \
1111
# RUN: | FileCheck -check-prefix=CHECK-INST %s
1212

13-
# CHECK-INST: qc.e.addai s1, -1
14-
# CHECK-ENC: encoding: [0x9f,0x24,0xff,0xff,0xff,0xff]
15-
qc.e.addai x9, 4294967295
13+
# CHECK-INST: qc.e.addai s1, 2147483647
14+
# CHECK-ENC: encoding: [0x9f,0x24,0xff,0xff,0xff,0x7f]
15+
qc.e.addai x9, 2147483647
1616

1717
# CHECK-INST: qc.e.addai s1, -2147483648
1818
# CHECK-ENC: encoding: [0x9f,0x24,0x00,0x00,0x00,0x80]
@@ -28,9 +28,9 @@ qc.e.addi x10, x9, -33554432
2828
qc.e.addi x10, x9, 33554431
2929

3030

31-
# CHECK-INST: qc.e.andai s1, -1
32-
# CHECK-ENC: encoding: [0x9f,0xa4,0xff,0xff,0xff,0xff]
33-
qc.e.andai x9, 4294967295
31+
# CHECK-INST: qc.e.andai s1, 2147483647
32+
# CHECK-ENC: encoding: [0x9f,0xa4,0xff,0xff,0xff,0x7f]
33+
qc.e.andai x9, 2147483647
3434

3535
# CHECK-INST: qc.e.andai s1, -2147483648
3636
# CHECK-ENC: encoding: [0x9f,0xa4,0x00,0x00,0x00,0x80]
@@ -46,9 +46,9 @@ qc.e.andi x10, x9, -33554432
4646
qc.e.andi x10, x9, 33554431
4747

4848

49-
# CHECK-INST: qc.e.orai s1, -1
50-
# CHECK-ENC: encoding: [0x9f,0x94,0xff,0xff,0xff,0xff]
51-
qc.e.orai x9, 4294967295
49+
# CHECK-INST: qc.e.orai s1, 2147483647
50+
# CHECK-ENC: encoding: [0x9f,0x94,0xff,0xff,0xff,0x7f]
51+
qc.e.orai x9, 2147483647
5252

5353
# CHECK-INST: qc.e.orai s1, -2147483648
5454
# CHECK-ENC: encoding: [0x9f,0x94,0x00,0x00,0x00,0x80]
@@ -64,9 +64,9 @@ qc.e.ori x10, x9, -33554432
6464
qc.e.ori x10, x9, 33554431
6565

6666

67-
# CHECK-INST: qc.e.xorai s1, -1
68-
# CHECK-ENC: encoding: [0x9f,0x14,0xff,0xff,0xff,0xff]
69-
qc.e.xorai x9, 4294967295
67+
# CHECK-INST: qc.e.xorai s1, 2147483647
68+
# CHECK-ENC: encoding: [0x9f,0x14,0xff,0xff,0xff,0x7f]
69+
qc.e.xorai x9, 2147483647
7070

7171
# CHECK-INST: qc.e.xorai s1, -2147483648
7272
# CHECK-ENC: encoding: [0x9f,0x14,0x00,0x00,0x00,0x80]

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