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[VPlan] Use State.get to extract lane mask for BranchOnMask.
Simplifies the code slightly and avoids redundant extracts/broadcasts if the operand is live-in or already scalar.
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9 files changed

+68
-152
lines changed

9 files changed

+68
-152
lines changed

‎llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp‎

Lines changed: 3 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -2444,16 +2444,12 @@ void VPScalarCastRecipe ::print(raw_ostream &O, const Twine &Indent,
24442444
void VPBranchOnMaskRecipe::execute(VPTransformState &State) {
24452445
assert(State.Lane && "Branch on Mask works only on single instance.");
24462446

2447-
unsigned Lane = State.Lane->getKnownLane();
24482447

24492448
Value *ConditionBit = nullptr;
24502449
VPValue *BlockInMask = getMask();
2451-
if (BlockInMask) {
2452-
ConditionBit = State.get(BlockInMask);
2453-
if (ConditionBit->getType()->isVectorTy())
2454-
ConditionBit = State.Builder.CreateExtractElement(
2455-
ConditionBit, State.Builder.getInt32(Lane));
2456-
} else // Block in mask is all-one.
2450+
if (BlockInMask)
2451+
ConditionBit = State.get(BlockInMask, *State.Lane);
2452+
else // Block in mask is all-one.
24572453
ConditionBit = State.Builder.getTrue();
24582454

24592455
// Replace the temporary unreachable terminator with a new conditional branch,

‎llvm/test/Transforms/LoopVectorize/AArch64/invariant-replicate-region.ll‎

Lines changed: 4 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -16,32 +16,28 @@ define i32 @test_invariant_replicate_region(i32 %x, i1 %c) {
1616
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
1717
; CHECK: [[VECTOR_BODY]]:
1818
; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_UREM_CONTINUE6:.*]] ]
19-
; CHECK-NEXT: [[TMP0:%.*]] = extractelement <4 x i1> [[BROADCAST_SPLAT]], i32 0
20-
; CHECK-NEXT: br i1 [[TMP0]], label %[[PRED_UREM_IF:.*]], label %[[PRED_UREM_CONTINUE:.*]]
19+
; CHECK-NEXT: br i1 [[C]], label %[[PRED_UREM_IF:.*]], label %[[PRED_UREM_CONTINUE:.*]]
2120
; CHECK: [[PRED_UREM_IF]]:
2221
; CHECK-NEXT: [[TMP1:%.*]] = urem i32 10, [[X]]
2322
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[TMP1]], i32 0
2423
; CHECK-NEXT: br label %[[PRED_UREM_CONTINUE]]
2524
; CHECK: [[PRED_UREM_CONTINUE]]:
2625
; CHECK-NEXT: [[TMP3:%.*]] = phi <4 x i32> [ poison, %[[VECTOR_BODY]] ], [ [[TMP2]], %[[PRED_UREM_IF]] ]
27-
; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i1> [[BROADCAST_SPLAT]], i32 1
28-
; CHECK-NEXT: br i1 [[TMP4]], label %[[PRED_UREM_IF1:.*]], label %[[PRED_UREM_CONTINUE2:.*]]
26+
; CHECK-NEXT: br i1 [[C]], label %[[PRED_UREM_IF1:.*]], label %[[PRED_UREM_CONTINUE2:.*]]
2927
; CHECK: [[PRED_UREM_IF1]]:
3028
; CHECK-NEXT: [[TMP5:%.*]] = urem i32 10, [[X]]
3129
; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[TMP5]], i32 1
3230
; CHECK-NEXT: br label %[[PRED_UREM_CONTINUE2]]
3331
; CHECK: [[PRED_UREM_CONTINUE2]]:
3432
; CHECK-NEXT: [[TMP7:%.*]] = phi <4 x i32> [ [[TMP3]], %[[PRED_UREM_CONTINUE]] ], [ [[TMP6]], %[[PRED_UREM_IF1]] ]
35-
; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x i1> [[BROADCAST_SPLAT]], i32 2
36-
; CHECK-NEXT: br i1 [[TMP8]], label %[[PRED_UREM_IF3:.*]], label %[[PRED_UREM_CONTINUE4:.*]]
33+
; CHECK-NEXT: br i1 [[C]], label %[[PRED_UREM_IF3:.*]], label %[[PRED_UREM_CONTINUE4:.*]]
3734
; CHECK: [[PRED_UREM_IF3]]:
3835
; CHECK-NEXT: [[TMP9:%.*]] = urem i32 10, [[X]]
3936
; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x i32> [[TMP7]], i32 [[TMP9]], i32 2
4037
; CHECK-NEXT: br label %[[PRED_UREM_CONTINUE4]]
4138
; CHECK: [[PRED_UREM_CONTINUE4]]:
4239
; CHECK-NEXT: [[TMP11:%.*]] = phi <4 x i32> [ [[TMP7]], %[[PRED_UREM_CONTINUE2]] ], [ [[TMP10]], %[[PRED_UREM_IF3]] ]
43-
; CHECK-NEXT: [[TMP12:%.*]] = extractelement <4 x i1> [[BROADCAST_SPLAT]], i32 3
44-
; CHECK-NEXT: br i1 [[TMP12]], label %[[PRED_UREM_IF5:.*]], label %[[PRED_UREM_CONTINUE6]]
40+
; CHECK-NEXT: br i1 [[C]], label %[[PRED_UREM_IF5:.*]], label %[[PRED_UREM_CONTINUE6]]
4541
; CHECK: [[PRED_UREM_IF5]]:
4642
; CHECK-NEXT: [[TMP13:%.*]] = urem i32 10, [[X]]
4743
; CHECK-NEXT: [[TMP14:%.*]] = insertelement <4 x i32> [[TMP11]], i32 [[TMP13]], i32 3

‎llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll‎

Lines changed: 8 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -209,50 +209,42 @@ define i32 @cost_of_exit_branch_and_cond_insts(ptr %a, ptr %b, i1 %c, i16 %x) #0
209209
; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE18:.*]] ]
210210
; CHECK-NEXT: [[TMP10:%.*]] = add i32 [[INDEX]], 0
211211
; CHECK-NEXT: [[TMP11:%.*]] = getelementptr i32, ptr [[B]], i32 [[TMP10]]
212-
; CHECK-NEXT: [[TMP12:%.*]] = extractelement <8 x i1> [[BROADCAST_SPLAT]], i32 0
213-
; CHECK-NEXT: br i1 [[TMP12]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]
212+
; CHECK-NEXT: br i1 [[C]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]
214213
; CHECK: [[PRED_STORE_IF]]:
215214
; CHECK-NEXT: store i1 false, ptr [[A]], align 1, !alias.scope [[META11:![0-9]+]], !noalias [[META14:![0-9]+]]
216215
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE]]
217216
; CHECK: [[PRED_STORE_CONTINUE]]:
218-
; CHECK-NEXT: [[TMP13:%.*]] = extractelement <8 x i1> [[BROADCAST_SPLAT]], i32 1
219-
; CHECK-NEXT: br i1 [[TMP13]], label %[[PRED_STORE_IF5:.*]], label %[[PRED_STORE_CONTINUE6:.*]]
217+
; CHECK-NEXT: br i1 [[C]], label %[[PRED_STORE_IF5:.*]], label %[[PRED_STORE_CONTINUE6:.*]]
220218
; CHECK: [[PRED_STORE_IF5]]:
221219
; CHECK-NEXT: store i1 false, ptr [[A]], align 1, !alias.scope [[META11]], !noalias [[META14]]
222220
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE6]]
223221
; CHECK: [[PRED_STORE_CONTINUE6]]:
224-
; CHECK-NEXT: [[TMP14:%.*]] = extractelement <8 x i1> [[BROADCAST_SPLAT]], i32 2
225-
; CHECK-NEXT: br i1 [[TMP14]], label %[[PRED_STORE_IF7:.*]], label %[[PRED_STORE_CONTINUE8:.*]]
222+
; CHECK-NEXT: br i1 [[C]], label %[[PRED_STORE_IF7:.*]], label %[[PRED_STORE_CONTINUE8:.*]]
226223
; CHECK: [[PRED_STORE_IF7]]:
227224
; CHECK-NEXT: store i1 false, ptr [[A]], align 1, !alias.scope [[META11]], !noalias [[META14]]
228225
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE8]]
229226
; CHECK: [[PRED_STORE_CONTINUE8]]:
230-
; CHECK-NEXT: [[TMP15:%.*]] = extractelement <8 x i1> [[BROADCAST_SPLAT]], i32 3
231-
; CHECK-NEXT: br i1 [[TMP15]], label %[[PRED_STORE_IF9:.*]], label %[[PRED_STORE_CONTINUE10:.*]]
227+
; CHECK-NEXT: br i1 [[C]], label %[[PRED_STORE_IF9:.*]], label %[[PRED_STORE_CONTINUE10:.*]]
232228
; CHECK: [[PRED_STORE_IF9]]:
233229
; CHECK-NEXT: store i1 false, ptr [[A]], align 1, !alias.scope [[META11]], !noalias [[META14]]
234230
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE10]]
235231
; CHECK: [[PRED_STORE_CONTINUE10]]:
236-
; CHECK-NEXT: [[TMP16:%.*]] = extractelement <8 x i1> [[BROADCAST_SPLAT]], i32 4
237-
; CHECK-NEXT: br i1 [[TMP16]], label %[[PRED_STORE_IF11:.*]], label %[[PRED_STORE_CONTINUE12:.*]]
232+
; CHECK-NEXT: br i1 [[C]], label %[[PRED_STORE_IF11:.*]], label %[[PRED_STORE_CONTINUE12:.*]]
238233
; CHECK: [[PRED_STORE_IF11]]:
239234
; CHECK-NEXT: store i1 false, ptr [[A]], align 1, !alias.scope [[META11]], !noalias [[META14]]
240235
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE12]]
241236
; CHECK: [[PRED_STORE_CONTINUE12]]:
242-
; CHECK-NEXT: [[TMP17:%.*]] = extractelement <8 x i1> [[BROADCAST_SPLAT]], i32 5
243-
; CHECK-NEXT: br i1 [[TMP17]], label %[[PRED_STORE_IF13:.*]], label %[[PRED_STORE_CONTINUE14:.*]]
237+
; CHECK-NEXT: br i1 [[C]], label %[[PRED_STORE_IF13:.*]], label %[[PRED_STORE_CONTINUE14:.*]]
244238
; CHECK: [[PRED_STORE_IF13]]:
245239
; CHECK-NEXT: store i1 false, ptr [[A]], align 1, !alias.scope [[META11]], !noalias [[META14]]
246240
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE14]]
247241
; CHECK: [[PRED_STORE_CONTINUE14]]:
248-
; CHECK-NEXT: [[TMP18:%.*]] = extractelement <8 x i1> [[BROADCAST_SPLAT]], i32 6
249-
; CHECK-NEXT: br i1 [[TMP18]], label %[[PRED_STORE_IF15:.*]], label %[[PRED_STORE_CONTINUE16:.*]]
242+
; CHECK-NEXT: br i1 [[C]], label %[[PRED_STORE_IF15:.*]], label %[[PRED_STORE_CONTINUE16:.*]]
250243
; CHECK: [[PRED_STORE_IF15]]:
251244
; CHECK-NEXT: store i1 false, ptr [[A]], align 1, !alias.scope [[META11]], !noalias [[META14]]
252245
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE16]]
253246
; CHECK: [[PRED_STORE_CONTINUE16]]:
254-
; CHECK-NEXT: [[TMP19:%.*]] = extractelement <8 x i1> [[BROADCAST_SPLAT]], i32 7
255-
; CHECK-NEXT: br i1 [[TMP19]], label %[[PRED_STORE_IF17:.*]], label %[[PRED_STORE_CONTINUE18]]
247+
; CHECK-NEXT: br i1 [[C]], label %[[PRED_STORE_IF17:.*]], label %[[PRED_STORE_CONTINUE18]]
256248
; CHECK: [[PRED_STORE_IF17]]:
257249
; CHECK-NEXT: store i1 false, ptr [[A]], align 1, !alias.scope [[META11]], !noalias [[META14]]
258250
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE18]]

‎llvm/test/Transforms/LoopVectorize/X86/load-deref-pred.ll‎

Lines changed: 16 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -524,143 +524,127 @@ define i32 @test_step_narrower_than_access(i64 %len, ptr %test_base) {
524524
; CHECK-NEXT: [[TMP61:%.*]] = insertelement <4 x i1> [[TMP60]], i1 [[TMP57]], i32 1
525525
; CHECK-NEXT: [[TMP62:%.*]] = insertelement <4 x i1> [[TMP61]], i1 [[TMP58]], i32 2
526526
; CHECK-NEXT: [[TMP63:%.*]] = insertelement <4 x i1> [[TMP62]], i1 [[TMP59]], i32 3
527-
; CHECK-NEXT: [[TMP64:%.*]] = extractelement <4 x i1> [[TMP39]], i32 0
528-
; CHECK-NEXT: br i1 [[TMP64]], label [[PRED_LOAD_IF:%.*]], label [[PRED_LOAD_CONTINUE:%.*]]
527+
; CHECK-NEXT: br i1 [[TMP32]], label [[PRED_LOAD_IF:%.*]], label [[PRED_LOAD_CONTINUE:%.*]]
529528
; CHECK: pred.load.if:
530529
; CHECK-NEXT: [[TMP65:%.*]] = getelementptr inbounds i16, ptr [[ALLOCA]], i64 [[TMP0]]
531530
; CHECK-NEXT: [[TMP66:%.*]] = load i32, ptr [[TMP65]], align 4
532531
; CHECK-NEXT: [[TMP67:%.*]] = insertelement <4 x i32> poison, i32 [[TMP66]], i32 0
533532
; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE]]
534533
; CHECK: pred.load.continue:
535534
; CHECK-NEXT: [[TMP68:%.*]] = phi <4 x i32> [ poison, [[VECTOR_BODY]] ], [ [[TMP67]], [[PRED_LOAD_IF]] ]
536-
; CHECK-NEXT: [[TMP69:%.*]] = extractelement <4 x i1> [[TMP39]], i32 1
537-
; CHECK-NEXT: br i1 [[TMP69]], label [[PRED_LOAD_IF4:%.*]], label [[PRED_LOAD_CONTINUE5:%.*]]
535+
; CHECK-NEXT: br i1 [[TMP33]], label [[PRED_LOAD_IF4:%.*]], label [[PRED_LOAD_CONTINUE5:%.*]]
538536
; CHECK: pred.load.if4:
539537
; CHECK-NEXT: [[TMP70:%.*]] = getelementptr inbounds i16, ptr [[ALLOCA]], i64 [[TMP1]]
540538
; CHECK-NEXT: [[TMP71:%.*]] = load i32, ptr [[TMP70]], align 4
541539
; CHECK-NEXT: [[TMP72:%.*]] = insertelement <4 x i32> [[TMP68]], i32 [[TMP71]], i32 1
542540
; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE5]]
543541
; CHECK: pred.load.continue5:
544542
; CHECK-NEXT: [[TMP73:%.*]] = phi <4 x i32> [ [[TMP68]], [[PRED_LOAD_CONTINUE]] ], [ [[TMP72]], [[PRED_LOAD_IF4]] ]
545-
; CHECK-NEXT: [[TMP74:%.*]] = extractelement <4 x i1> [[TMP39]], i32 2
546-
; CHECK-NEXT: br i1 [[TMP74]], label [[PRED_LOAD_IF6:%.*]], label [[PRED_LOAD_CONTINUE7:%.*]]
543+
; CHECK-NEXT: br i1 [[TMP34]], label [[PRED_LOAD_IF6:%.*]], label [[PRED_LOAD_CONTINUE7:%.*]]
547544
; CHECK: pred.load.if6:
548545
; CHECK-NEXT: [[TMP75:%.*]] = getelementptr inbounds i16, ptr [[ALLOCA]], i64 [[TMP2]]
549546
; CHECK-NEXT: [[TMP76:%.*]] = load i32, ptr [[TMP75]], align 4
550547
; CHECK-NEXT: [[TMP77:%.*]] = insertelement <4 x i32> [[TMP73]], i32 [[TMP76]], i32 2
551548
; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE7]]
552549
; CHECK: pred.load.continue7:
553550
; CHECK-NEXT: [[TMP78:%.*]] = phi <4 x i32> [ [[TMP73]], [[PRED_LOAD_CONTINUE5]] ], [ [[TMP77]], [[PRED_LOAD_IF6]] ]
554-
; CHECK-NEXT: [[TMP79:%.*]] = extractelement <4 x i1> [[TMP39]], i32 3
555-
; CHECK-NEXT: br i1 [[TMP79]], label [[PRED_LOAD_IF8:%.*]], label [[PRED_LOAD_CONTINUE9:%.*]]
551+
; CHECK-NEXT: br i1 [[TMP35]], label [[PRED_LOAD_IF8:%.*]], label [[PRED_LOAD_CONTINUE9:%.*]]
556552
; CHECK: pred.load.if8:
557553
; CHECK-NEXT: [[TMP80:%.*]] = getelementptr inbounds i16, ptr [[ALLOCA]], i64 [[TMP3]]
558554
; CHECK-NEXT: [[TMP81:%.*]] = load i32, ptr [[TMP80]], align 4
559555
; CHECK-NEXT: [[TMP82:%.*]] = insertelement <4 x i32> [[TMP78]], i32 [[TMP81]], i32 3
560556
; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE9]]
561557
; CHECK: pred.load.continue9:
562558
; CHECK-NEXT: [[TMP83:%.*]] = phi <4 x i32> [ [[TMP78]], [[PRED_LOAD_CONTINUE7]] ], [ [[TMP82]], [[PRED_LOAD_IF8]] ]
563-
; CHECK-NEXT: [[TMP84:%.*]] = extractelement <4 x i1> [[TMP47]], i32 0
564-
; CHECK-NEXT: br i1 [[TMP84]], label [[PRED_LOAD_IF10:%.*]], label [[PRED_LOAD_CONTINUE11:%.*]]
559+
; CHECK-NEXT: br i1 [[TMP40]], label [[PRED_LOAD_IF10:%.*]], label [[PRED_LOAD_CONTINUE11:%.*]]
565560
; CHECK: pred.load.if10:
566561
; CHECK-NEXT: [[TMP85:%.*]] = getelementptr inbounds i16, ptr [[ALLOCA]], i64 [[TMP4]]
567562
; CHECK-NEXT: [[TMP86:%.*]] = load i32, ptr [[TMP85]], align 4
568563
; CHECK-NEXT: [[TMP87:%.*]] = insertelement <4 x i32> poison, i32 [[TMP86]], i32 0
569564
; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE11]]
570565
; CHECK: pred.load.continue11:
571566
; CHECK-NEXT: [[TMP88:%.*]] = phi <4 x i32> [ poison, [[PRED_LOAD_CONTINUE9]] ], [ [[TMP87]], [[PRED_LOAD_IF10]] ]
572-
; CHECK-NEXT: [[TMP89:%.*]] = extractelement <4 x i1> [[TMP47]], i32 1
573-
; CHECK-NEXT: br i1 [[TMP89]], label [[PRED_LOAD_IF12:%.*]], label [[PRED_LOAD_CONTINUE13:%.*]]
567+
; CHECK-NEXT: br i1 [[TMP41]], label [[PRED_LOAD_IF12:%.*]], label [[PRED_LOAD_CONTINUE13:%.*]]
574568
; CHECK: pred.load.if12:
575569
; CHECK-NEXT: [[TMP90:%.*]] = getelementptr inbounds i16, ptr [[ALLOCA]], i64 [[TMP5]]
576570
; CHECK-NEXT: [[TMP91:%.*]] = load i32, ptr [[TMP90]], align 4
577571
; CHECK-NEXT: [[TMP92:%.*]] = insertelement <4 x i32> [[TMP88]], i32 [[TMP91]], i32 1
578572
; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE13]]
579573
; CHECK: pred.load.continue13:
580574
; CHECK-NEXT: [[TMP93:%.*]] = phi <4 x i32> [ [[TMP88]], [[PRED_LOAD_CONTINUE11]] ], [ [[TMP92]], [[PRED_LOAD_IF12]] ]
581-
; CHECK-NEXT: [[TMP94:%.*]] = extractelement <4 x i1> [[TMP47]], i32 2
582-
; CHECK-NEXT: br i1 [[TMP94]], label [[PRED_LOAD_IF14:%.*]], label [[PRED_LOAD_CONTINUE15:%.*]]
575+
; CHECK-NEXT: br i1 [[TMP42]], label [[PRED_LOAD_IF14:%.*]], label [[PRED_LOAD_CONTINUE15:%.*]]
583576
; CHECK: pred.load.if14:
584577
; CHECK-NEXT: [[TMP95:%.*]] = getelementptr inbounds i16, ptr [[ALLOCA]], i64 [[TMP6]]
585578
; CHECK-NEXT: [[TMP96:%.*]] = load i32, ptr [[TMP95]], align 4
586579
; CHECK-NEXT: [[TMP97:%.*]] = insertelement <4 x i32> [[TMP93]], i32 [[TMP96]], i32 2
587580
; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE15]]
588581
; CHECK: pred.load.continue15:
589582
; CHECK-NEXT: [[TMP98:%.*]] = phi <4 x i32> [ [[TMP93]], [[PRED_LOAD_CONTINUE13]] ], [ [[TMP97]], [[PRED_LOAD_IF14]] ]
590-
; CHECK-NEXT: [[TMP99:%.*]] = extractelement <4 x i1> [[TMP47]], i32 3
591-
; CHECK-NEXT: br i1 [[TMP99]], label [[PRED_LOAD_IF16:%.*]], label [[PRED_LOAD_CONTINUE17:%.*]]
583+
; CHECK-NEXT: br i1 [[TMP43]], label [[PRED_LOAD_IF16:%.*]], label [[PRED_LOAD_CONTINUE17:%.*]]
592584
; CHECK: pred.load.if16:
593585
; CHECK-NEXT: [[TMP100:%.*]] = getelementptr inbounds i16, ptr [[ALLOCA]], i64 [[TMP7]]
594586
; CHECK-NEXT: [[TMP101:%.*]] = load i32, ptr [[TMP100]], align 4
595587
; CHECK-NEXT: [[TMP102:%.*]] = insertelement <4 x i32> [[TMP98]], i32 [[TMP101]], i32 3
596588
; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE17]]
597589
; CHECK: pred.load.continue17:
598590
; CHECK-NEXT: [[TMP103:%.*]] = phi <4 x i32> [ [[TMP98]], [[PRED_LOAD_CONTINUE15]] ], [ [[TMP102]], [[PRED_LOAD_IF16]] ]
599-
; CHECK-NEXT: [[TMP104:%.*]] = extractelement <4 x i1> [[TMP55]], i32 0
600-
; CHECK-NEXT: br i1 [[TMP104]], label [[PRED_LOAD_IF18:%.*]], label [[PRED_LOAD_CONTINUE19:%.*]]
591+
; CHECK-NEXT: br i1 [[TMP48]], label [[PRED_LOAD_IF18:%.*]], label [[PRED_LOAD_CONTINUE19:%.*]]
601592
; CHECK: pred.load.if18:
602593
; CHECK-NEXT: [[TMP105:%.*]] = getelementptr inbounds i16, ptr [[ALLOCA]], i64 [[TMP8]]
603594
; CHECK-NEXT: [[TMP106:%.*]] = load i32, ptr [[TMP105]], align 4
604595
; CHECK-NEXT: [[TMP107:%.*]] = insertelement <4 x i32> poison, i32 [[TMP106]], i32 0
605596
; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE19]]
606597
; CHECK: pred.load.continue19:
607598
; CHECK-NEXT: [[TMP108:%.*]] = phi <4 x i32> [ poison, [[PRED_LOAD_CONTINUE17]] ], [ [[TMP107]], [[PRED_LOAD_IF18]] ]
608-
; CHECK-NEXT: [[TMP109:%.*]] = extractelement <4 x i1> [[TMP55]], i32 1
609-
; CHECK-NEXT: br i1 [[TMP109]], label [[PRED_LOAD_IF20:%.*]], label [[PRED_LOAD_CONTINUE21:%.*]]
599+
; CHECK-NEXT: br i1 [[TMP49]], label [[PRED_LOAD_IF20:%.*]], label [[PRED_LOAD_CONTINUE21:%.*]]
610600
; CHECK: pred.load.if20:
611601
; CHECK-NEXT: [[TMP110:%.*]] = getelementptr inbounds i16, ptr [[ALLOCA]], i64 [[TMP9]]
612602
; CHECK-NEXT: [[TMP111:%.*]] = load i32, ptr [[TMP110]], align 4
613603
; CHECK-NEXT: [[TMP112:%.*]] = insertelement <4 x i32> [[TMP108]], i32 [[TMP111]], i32 1
614604
; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE21]]
615605
; CHECK: pred.load.continue21:
616606
; CHECK-NEXT: [[TMP113:%.*]] = phi <4 x i32> [ [[TMP108]], [[PRED_LOAD_CONTINUE19]] ], [ [[TMP112]], [[PRED_LOAD_IF20]] ]
617-
; CHECK-NEXT: [[TMP114:%.*]] = extractelement <4 x i1> [[TMP55]], i32 2
618-
; CHECK-NEXT: br i1 [[TMP114]], label [[PRED_LOAD_IF22:%.*]], label [[PRED_LOAD_CONTINUE23:%.*]]
607+
; CHECK-NEXT: br i1 [[TMP50]], label [[PRED_LOAD_IF22:%.*]], label [[PRED_LOAD_CONTINUE23:%.*]]
619608
; CHECK: pred.load.if22:
620609
; CHECK-NEXT: [[TMP115:%.*]] = getelementptr inbounds i16, ptr [[ALLOCA]], i64 [[TMP10]]
621610
; CHECK-NEXT: [[TMP116:%.*]] = load i32, ptr [[TMP115]], align 4
622611
; CHECK-NEXT: [[TMP117:%.*]] = insertelement <4 x i32> [[TMP113]], i32 [[TMP116]], i32 2
623612
; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE23]]
624613
; CHECK: pred.load.continue23:
625614
; CHECK-NEXT: [[TMP118:%.*]] = phi <4 x i32> [ [[TMP113]], [[PRED_LOAD_CONTINUE21]] ], [ [[TMP117]], [[PRED_LOAD_IF22]] ]
626-
; CHECK-NEXT: [[TMP119:%.*]] = extractelement <4 x i1> [[TMP55]], i32 3
627-
; CHECK-NEXT: br i1 [[TMP119]], label [[PRED_LOAD_IF24:%.*]], label [[PRED_LOAD_CONTINUE25:%.*]]
615+
; CHECK-NEXT: br i1 [[TMP51]], label [[PRED_LOAD_IF24:%.*]], label [[PRED_LOAD_CONTINUE25:%.*]]
628616
; CHECK: pred.load.if24:
629617
; CHECK-NEXT: [[TMP120:%.*]] = getelementptr inbounds i16, ptr [[ALLOCA]], i64 [[TMP11]]
630618
; CHECK-NEXT: [[TMP121:%.*]] = load i32, ptr [[TMP120]], align 4
631619
; CHECK-NEXT: [[TMP122:%.*]] = insertelement <4 x i32> [[TMP118]], i32 [[TMP121]], i32 3
632620
; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE25]]
633621
; CHECK: pred.load.continue25:
634622
; CHECK-NEXT: [[TMP123:%.*]] = phi <4 x i32> [ [[TMP118]], [[PRED_LOAD_CONTINUE23]] ], [ [[TMP122]], [[PRED_LOAD_IF24]] ]
635-
; CHECK-NEXT: [[TMP124:%.*]] = extractelement <4 x i1> [[TMP63]], i32 0
636-
; CHECK-NEXT: br i1 [[TMP124]], label [[PRED_LOAD_IF26:%.*]], label [[PRED_LOAD_CONTINUE27:%.*]]
623+
; CHECK-NEXT: br i1 [[TMP56]], label [[PRED_LOAD_IF26:%.*]], label [[PRED_LOAD_CONTINUE27:%.*]]
637624
; CHECK: pred.load.if26:
638625
; CHECK-NEXT: [[TMP125:%.*]] = getelementptr inbounds i16, ptr [[ALLOCA]], i64 [[TMP12]]
639626
; CHECK-NEXT: [[TMP126:%.*]] = load i32, ptr [[TMP125]], align 4
640627
; CHECK-NEXT: [[TMP127:%.*]] = insertelement <4 x i32> poison, i32 [[TMP126]], i32 0
641628
; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE27]]
642629
; CHECK: pred.load.continue27:
643630
; CHECK-NEXT: [[TMP128:%.*]] = phi <4 x i32> [ poison, [[PRED_LOAD_CONTINUE25]] ], [ [[TMP127]], [[PRED_LOAD_IF26]] ]
644-
; CHECK-NEXT: [[TMP129:%.*]] = extractelement <4 x i1> [[TMP63]], i32 1
645-
; CHECK-NEXT: br i1 [[TMP129]], label [[PRED_LOAD_IF28:%.*]], label [[PRED_LOAD_CONTINUE29:%.*]]
631+
; CHECK-NEXT: br i1 [[TMP57]], label [[PRED_LOAD_IF28:%.*]], label [[PRED_LOAD_CONTINUE29:%.*]]
646632
; CHECK: pred.load.if28:
647633
; CHECK-NEXT: [[TMP130:%.*]] = getelementptr inbounds i16, ptr [[ALLOCA]], i64 [[TMP13]]
648634
; CHECK-NEXT: [[TMP131:%.*]] = load i32, ptr [[TMP130]], align 4
649635
; CHECK-NEXT: [[TMP132:%.*]] = insertelement <4 x i32> [[TMP128]], i32 [[TMP131]], i32 1
650636
; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE29]]
651637
; CHECK: pred.load.continue29:
652638
; CHECK-NEXT: [[TMP133:%.*]] = phi <4 x i32> [ [[TMP128]], [[PRED_LOAD_CONTINUE27]] ], [ [[TMP132]], [[PRED_LOAD_IF28]] ]
653-
; CHECK-NEXT: [[TMP134:%.*]] = extractelement <4 x i1> [[TMP63]], i32 2
654-
; CHECK-NEXT: br i1 [[TMP134]], label [[PRED_LOAD_IF30:%.*]], label [[PRED_LOAD_CONTINUE31:%.*]]
639+
; CHECK-NEXT: br i1 [[TMP58]], label [[PRED_LOAD_IF30:%.*]], label [[PRED_LOAD_CONTINUE31:%.*]]
655640
; CHECK: pred.load.if30:
656641
; CHECK-NEXT: [[TMP135:%.*]] = getelementptr inbounds i16, ptr [[ALLOCA]], i64 [[TMP14]]
657642
; CHECK-NEXT: [[TMP136:%.*]] = load i32, ptr [[TMP135]], align 4
658643
; CHECK-NEXT: [[TMP137:%.*]] = insertelement <4 x i32> [[TMP133]], i32 [[TMP136]], i32 2
659644
; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE31]]
660645
; CHECK: pred.load.continue31:
661646
; CHECK-NEXT: [[TMP138:%.*]] = phi <4 x i32> [ [[TMP133]], [[PRED_LOAD_CONTINUE29]] ], [ [[TMP137]], [[PRED_LOAD_IF30]] ]
662-
; CHECK-NEXT: [[TMP139:%.*]] = extractelement <4 x i1> [[TMP63]], i32 3
663-
; CHECK-NEXT: br i1 [[TMP139]], label [[PRED_LOAD_IF32:%.*]], label [[PRED_LOAD_CONTINUE33]]
647+
; CHECK-NEXT: br i1 [[TMP59]], label [[PRED_LOAD_IF32:%.*]], label [[PRED_LOAD_CONTINUE33]]
664648
; CHECK: pred.load.if32:
665649
; CHECK-NEXT: [[TMP140:%.*]] = getelementptr inbounds i16, ptr [[ALLOCA]], i64 [[TMP15]]
666650
; CHECK-NEXT: [[TMP141:%.*]] = load i32, ptr [[TMP140]], align 4

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