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lukel97lukel97
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Move pass to just after RISCVVectorPeephole
1 parent e46afef commit 7152791

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55 files changed

+2018
-2363
lines changed

‎llvm/lib/Target/RISCV/RISCVTargetMachine.cpp‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -588,6 +588,8 @@ void RISCVPassConfig::addPreEmitPass2() {
588588

589589
void RISCVPassConfig::addMachineSSAOptimization() {
590590
addPass(createRISCVVectorPeepholePass());
591+
// TODO: Move this to pre regalloc
592+
addPass(createRISCVVMV0EliminationPass());
591593

592594
TargetPassConfig::addMachineSSAOptimization();
593595

@@ -600,6 +602,10 @@ void RISCVPassConfig::addMachineSSAOptimization() {
600602
}
601603

602604
void RISCVPassConfig::addPreRegAlloc() {
605+
// TODO: Move this as late as possible before regalloc
606+
if (TM->getOptLevel() == CodeGenOptLevel::None)
607+
addPass(createRISCVVMV0EliminationPass());
608+
603609
addPass(createRISCVPreRAExpandPseudoPass());
604610
if (TM->getOptLevel() != CodeGenOptLevel::None) {
605611
addPass(createRISCVMergeBaseOffsetOptPass());
@@ -613,8 +619,6 @@ void RISCVPassConfig::addPreRegAlloc() {
613619

614620
if (TM->getOptLevel() != CodeGenOptLevel::None && EnableMachinePipeliner)
615621
addPass(&MachinePipelinerID);
616-
617-
addPass(createRISCVVMV0EliminationPass());
618622
}
619623

620624
void RISCVPassConfig::addFastRegAlloc() {

‎llvm/test/CodeGen/RISCV/O0-pipeline.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -39,11 +39,11 @@
3939
; CHECK-NEXT: RISC-V DAG->DAG Pattern Instruction Selection
4040
; CHECK-NEXT: Finalize ISel and expand pseudo-instructions
4141
; CHECK-NEXT: Local Stack Slot Allocation
42+
; CHECK-NEXT: RISC-V VMV0 Elimination
4243
; CHECK-NEXT: RISC-V Pre-RA pseudo instruction expansion pass
4344
; CHECK-NEXT: RISC-V Insert Read/Write CSR Pass
4445
; CHECK-NEXT: RISC-V Insert Write VXRM Pass
4546
; CHECK-NEXT: RISC-V Landing Pad Setup
46-
; CHECK-NEXT: RISC-V VMV0 Elimination
4747
; CHECK-NEXT: Init Undef Pass
4848
; CHECK-NEXT: Eliminate PHI nodes for register allocation
4949
; CHECK-NEXT: Two-Address instruction pass

‎llvm/test/CodeGen/RISCV/O3-pipeline.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -97,6 +97,7 @@
9797
; CHECK-NEXT: RISC-V DAG->DAG Pattern Instruction Selection
9898
; CHECK-NEXT: Finalize ISel and expand pseudo-instructions
9999
; CHECK-NEXT: RISC-V Vector Peephole Optimization
100+
; CHECK-NEXT: RISC-V VMV0 Elimination
100101
; CHECK-NEXT: Lazy Machine Block Frequency Analysis
101102
; CHECK-NEXT: Early Tail Duplication
102103
; CHECK-NEXT: Optimize machine instruction PHIs
@@ -127,7 +128,6 @@
127128
; CHECK-NEXT: RISC-V Insert Read/Write CSR Pass
128129
; CHECK-NEXT: RISC-V Insert Write VXRM Pass
129130
; CHECK-NEXT: RISC-V Landing Pad Setup
130-
; CHECK-NEXT: RISC-V VMV0 Elimination
131131
; CHECK-NEXT: Detect Dead Lanes
132132
; CHECK-NEXT: Init Undef Pass
133133
; CHECK-NEXT: Process Implicit Definitions

‎llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll‎

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -3065,27 +3065,27 @@ define <vscale x 64 x i16> @vp_bitreverse_nxv64i16(<vscale x 64 x i16> %va, <vsc
30653065
; CHECK-NEXT: add a1, sp, a1
30663066
; CHECK-NEXT: addi a1, a1, 16
30673067
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
3068-
; CHECK-NEXT: csrr a3, vlenb
3068+
; CHECK-NEXT: csrr a4, vlenb
30693069
; CHECK-NEXT: lui a1, 1
30703070
; CHECK-NEXT: lui a2, 3
3071-
; CHECK-NEXT: srli a4, a3, 1
3072-
; CHECK-NEXT: slli a3, a3, 2
3073-
; CHECK-NEXT: vslidedown.vx v0, v0, a4
3074-
; CHECK-NEXT: sub a4, a0, a3
3075-
; CHECK-NEXT: sltu a5, a0, a4
3071+
; CHECK-NEXT: srli a3, a4, 1
3072+
; CHECK-NEXT: slli a4, a4, 2
3073+
; CHECK-NEXT: vslidedown.vx v0, v0, a3
3074+
; CHECK-NEXT: sub a3, a0, a4
3075+
; CHECK-NEXT: sltu a5, a0, a3
30763076
; CHECK-NEXT: addi a5, a5, -1
3077-
; CHECK-NEXT: and a5, a5, a4
3077+
; CHECK-NEXT: and a5, a5, a3
30783078
; CHECK-NEXT: lui a6, 5
3079-
; CHECK-NEXT: addi a4, a1, -241
3079+
; CHECK-NEXT: addi a3, a1, -241
30803080
; CHECK-NEXT: addi a2, a2, 819
30813081
; CHECK-NEXT: addi a1, a6, 1365
30823082
; CHECK-NEXT: vsetvli zero, a5, e16, m8, ta, ma
30833083
; CHECK-NEXT: vsrl.vi v8, v16, 8, v0.t
30843084
; CHECK-NEXT: vsll.vi v16, v16, 8, v0.t
30853085
; CHECK-NEXT: vor.vv v8, v16, v8, v0.t
30863086
; CHECK-NEXT: vsrl.vi v16, v8, 4, v0.t
3087-
; CHECK-NEXT: vand.vx v16, v16, a4, v0.t
3088-
; CHECK-NEXT: vand.vx v8, v8, a4, v0.t
3087+
; CHECK-NEXT: vand.vx v16, v16, a3, v0.t
3088+
; CHECK-NEXT: vand.vx v8, v8, a3, v0.t
30893089
; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
30903090
; CHECK-NEXT: vor.vv v8, v16, v8, v0.t
30913091
; CHECK-NEXT: vsrl.vi v16, v8, 2, v0.t
@@ -3100,23 +3100,23 @@ define <vscale x 64 x i16> @vp_bitreverse_nxv64i16(<vscale x 64 x i16> %va, <vsc
31003100
; CHECK-NEXT: vor.vv v8, v16, v8, v0.t
31013101
; CHECK-NEXT: addi a5, sp, 16
31023102
; CHECK-NEXT: vs8r.v v8, (a5) # Unknown-size Folded Spill
3103-
; CHECK-NEXT: bltu a0, a3, .LBB46_2
3103+
; CHECK-NEXT: bltu a0, a4, .LBB46_2
31043104
; CHECK-NEXT: # %bb.1:
3105-
; CHECK-NEXT: mv a0, a3
3105+
; CHECK-NEXT: mv a0, a4
31063106
; CHECK-NEXT: .LBB46_2:
31073107
; CHECK-NEXT: vmv1r.v v0, v24
3108-
; CHECK-NEXT: csrr a3, vlenb
3109-
; CHECK-NEXT: slli a3, a3, 3
3110-
; CHECK-NEXT: add a3, sp, a3
3111-
; CHECK-NEXT: addi a3, a3, 16
3112-
; CHECK-NEXT: vl8r.v v8, (a3) # Unknown-size Folded Reload
3108+
; CHECK-NEXT: csrr a4, vlenb
3109+
; CHECK-NEXT: slli a4, a4, 3
3110+
; CHECK-NEXT: add a4, sp, a4
3111+
; CHECK-NEXT: addi a4, a4, 16
3112+
; CHECK-NEXT: vl8r.v v16, (a4) # Unknown-size Folded Reload
31133113
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
3114-
; CHECK-NEXT: vsrl.vi v16, v8, 8, v0.t
3115-
; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
3116-
; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
3114+
; CHECK-NEXT: vsrl.vi v8, v16, 8, v0.t
3115+
; CHECK-NEXT: vsll.vi v16, v16, 8, v0.t
3116+
; CHECK-NEXT: vor.vv v8, v16, v8, v0.t
31173117
; CHECK-NEXT: vsrl.vi v16, v8, 4, v0.t
3118-
; CHECK-NEXT: vand.vx v16, v16, a4, v0.t
3119-
; CHECK-NEXT: vand.vx v8, v8, a4, v0.t
3118+
; CHECK-NEXT: vand.vx v16, v16, a3, v0.t
3119+
; CHECK-NEXT: vand.vx v8, v8, a3, v0.t
31203120
; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
31213121
; CHECK-NEXT: vor.vv v8, v16, v8, v0.t
31223122
; CHECK-NEXT: vsrl.vi v16, v8, 2, v0.t

‎llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll‎

Lines changed: 32 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -1498,55 +1498,66 @@ define <vscale x 16 x double> @vp_ceil_vv_nxv16f64(<vscale x 16 x double> %va, <
14981498
; CHECK-NEXT: addi sp, sp, -16
14991499
; CHECK-NEXT: .cfi_def_cfa_offset 16
15001500
; CHECK-NEXT: csrr a1, vlenb
1501-
; CHECK-NEXT: slli a1, a1, 3
1501+
; CHECK-NEXT: slli a1, a1, 4
15021502
; CHECK-NEXT: sub sp, sp, a1
1503-
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
1503+
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
15041504
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
1505-
; CHECK-NEXT: vmv1r.v v7, v0
1505+
; CHECK-NEXT: vmv1r.v v24, v0
1506+
; CHECK-NEXT: addi a1, sp, 16
1507+
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
15061508
; CHECK-NEXT: csrr a1, vlenb
15071509
; CHECK-NEXT: lui a2, %hi(.LCPI44_0)
15081510
; CHECK-NEXT: srli a3, a1, 3
15091511
; CHECK-NEXT: fld fa5, %lo(.LCPI44_0)(a2)
15101512
; CHECK-NEXT: sub a2, a0, a1
1511-
; CHECK-NEXT: vslidedown.vx v6, v0, a3
1513+
; CHECK-NEXT: vslidedown.vx v25, v0, a3
15121514
; CHECK-NEXT: sltu a3, a0, a2
15131515
; CHECK-NEXT: addi a3, a3, -1
15141516
; CHECK-NEXT: and a2, a3, a2
1515-
; CHECK-NEXT: vmv1r.v v0, v6
1517+
; CHECK-NEXT: vmv1r.v v0, v25
15161518
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
1517-
; CHECK-NEXT: vfabs.v v24, v16, v0.t
1518-
; CHECK-NEXT: addi a2, sp, 16
1519-
; CHECK-NEXT: vs8r.v v24, (a2) # Unknown-size Folded Spill
1520-
; CHECK-NEXT: vl8r.v v24, (a2) # Unknown-size Folded Reload
1519+
; CHECK-NEXT: vfabs.v v8, v16, v0.t
15211520
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
1522-
; CHECK-NEXT: vmflt.vf v6, v24, fa5, v0.t
1521+
; CHECK-NEXT: vmflt.vf v25, v8, fa5, v0.t
15231522
; CHECK-NEXT: fsrmi a2, 3
1524-
; CHECK-NEXT: vmv1r.v v0, v6
1523+
; CHECK-NEXT: vmv1r.v v0, v25
15251524
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
1526-
; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
1525+
; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t
15271526
; CHECK-NEXT: fsrm a2
1528-
; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t
1527+
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
15291528
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
1530-
; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t
1529+
; CHECK-NEXT: vfsgnj.vv v16, v8, v16, v0.t
1530+
; CHECK-NEXT: csrr a2, vlenb
1531+
; CHECK-NEXT: slli a2, a2, 3
1532+
; CHECK-NEXT: add a2, sp, a2
1533+
; CHECK-NEXT: addi a2, a2, 16
1534+
; CHECK-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill
15311535
; CHECK-NEXT: bltu a0, a1, .LBB44_2
15321536
; CHECK-NEXT: # %bb.1:
15331537
; CHECK-NEXT: mv a0, a1
15341538
; CHECK-NEXT: .LBB44_2:
1535-
; CHECK-NEXT: vmv1r.v v0, v7
1539+
; CHECK-NEXT: vmv1r.v v0, v24
1540+
; CHECK-NEXT: addi a1, sp, 16
1541+
; CHECK-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
15361542
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
1537-
; CHECK-NEXT: vfabs.v v24, v8, v0.t
1543+
; CHECK-NEXT: vfabs.v v16, v8, v0.t
15381544
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
1539-
; CHECK-NEXT: vmflt.vf v7, v24, fa5, v0.t
1545+
; CHECK-NEXT: vmflt.vf v24, v16, fa5, v0.t
15401546
; CHECK-NEXT: fsrmi a0, 3
1541-
; CHECK-NEXT: vmv1r.v v0, v7
1547+
; CHECK-NEXT: vmv1r.v v0, v24
15421548
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
1543-
; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t
1549+
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
15441550
; CHECK-NEXT: fsrm a0
1545-
; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t
1551+
; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
15461552
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
1547-
; CHECK-NEXT: vfsgnj.vv v8, v24, v8, v0.t
1553+
; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t
15481554
; CHECK-NEXT: csrr a0, vlenb
15491555
; CHECK-NEXT: slli a0, a0, 3
1556+
; CHECK-NEXT: add a0, sp, a0
1557+
; CHECK-NEXT: addi a0, a0, 16
1558+
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
1559+
; CHECK-NEXT: csrr a0, vlenb
1560+
; CHECK-NEXT: slli a0, a0, 4
15501561
; CHECK-NEXT: add sp, sp, a0
15511562
; CHECK-NEXT: .cfi_def_cfa sp, 16
15521563
; CHECK-NEXT: addi sp, sp, 16

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