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1 | 1 | ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 |
2 | 2 | ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s |
3 | 3 |
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4 | | -define amdgpu_ps i32 @bcnt032_not_for_vregs(i64 %val) { |
| 4 | +define i32 @bcnt032_not_for_vregs(i32 %val0) { |
5 | 5 | ; CHECK-LABEL: bcnt032_not_for_vregs: |
6 | 6 | ; CHECK: ; %bb.0: |
| 7 | +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
7 | 8 | ; CHECK-NEXT: v_bcnt_u32_b32 v0, v0, 0 |
8 | | -; CHECK-NEXT: v_sub_u32_e32 v0, 32, v0 |
9 | | -; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 |
10 | | -; CHECK-NEXT: ;;#ASMSTART |
11 | | -; CHECK-NEXT: ; use v0 |
12 | | -; CHECK-NEXT: ;;#ASMEND |
| 9 | +; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 32, v0 |
13 | 10 | ; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc |
14 | | -; CHECK-NEXT: v_readfirstlane_b32 s0, v0 |
15 | | -; CHECK-NEXT: ; return to shader part epilog |
16 | | - %val0 = trunc i64 %val to i32 |
| 11 | +; CHECK-NEXT: s_setpc_b64 s[30:31] |
17 | 12 | %result = call i32 @llvm.ctpop.i32(i32 %val0) |
18 | 13 | %result2 = sub i32 32, %result |
19 | | - call void asm "; use $0", "s"(i32 %result2) |
20 | 14 | %cmp = icmp ne i32 %result2, 0 |
21 | 15 | %zext = zext i1 %cmp to i32 |
22 | 16 | ret i32 %zext |
23 | 17 | } |
24 | 18 |
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25 | | -define amdgpu_ps i32 @bcnt064_not_for_vregs(i64 %val0) { |
| 19 | +define i32 @bcnt064_not_for_vregs(i64 %val0) { |
26 | 20 | ; CHECK-LABEL: bcnt064_not_for_vregs: |
27 | 21 | ; CHECK: ; %bb.0: |
| 22 | +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
28 | 23 | ; CHECK-NEXT: v_bcnt_u32_b32 v0, v0, 0 |
29 | 24 | ; CHECK-NEXT: v_bcnt_u32_b32 v0, v1, v0 |
30 | | -; CHECK-NEXT: v_sub_co_u32_e32 v0, vcc, 64, v0 |
31 | | -; CHECK-NEXT: v_subb_co_u32_e64 v1, s[0:1], 0, 0, vcc |
32 | | -; CHECK-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1] |
33 | | -; CHECK-NEXT: ;;#ASMSTART |
34 | | -; CHECK-NEXT: ; use v[0:1] |
35 | | -; CHECK-NEXT: ;;#ASMEND |
| 25 | +; CHECK-NEXT: v_mov_b32_e32 v1, 0 |
| 26 | +; CHECK-NEXT: v_cmp_ne_u64_e32 vcc, 64, v[0:1] |
36 | 27 | ; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc |
37 | | -; CHECK-NEXT: v_readfirstlane_b32 s0, v0 |
38 | | -; CHECK-NEXT: ; return to shader part epilog |
| 28 | +; CHECK-NEXT: s_setpc_b64 s[30:31] |
39 | 29 | %result = call i64 @llvm.ctpop.i64(i64 %val0) |
40 | 30 | %result2 = sub i64 64, %result |
41 | | - call void asm "; use $0", "s"(i64 %result2) |
42 | 31 | %cmp = icmp ne i64 %result2, 0 |
43 | 32 | %zext = zext i1 %cmp to i32 |
44 | 33 | ret i32 %zext |
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