[SDAG] Apply or-disjoint in SelectionDAG::isBaseWithConstantOffset (#88493)

Signed-off-by: feng.feng <[email protected]>

Author: fengfeng09

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

@@ -5203,15 +5203,8 @@ bool SelectionDAG::isADDLike(SDValue Op) const {
 }
 
 bool SelectionDAG::isBaseWithConstantOffset(SDValue Op) const {
-  if ((Op.getOpcode() != ISD::ADD && Op.getOpcode() != ISD::OR) ||
-      !isa<ConstantSDNode>(Op.getOperand(1)))
-    return false;
-
-  if (Op.getOpcode() == ISD::OR &&
-      !MaskedValueIsZero(Op.getOperand(0), Op.getConstantOperandAPInt(1)))
-    return false;
-
-  return true;
+  return Op.getNumOperands() == 2 && isa<ConstantSDNode>(Op.getOperand(1)) &&
+         (Op.getOpcode() == ISD::ADD || isADDLike(Op));
 }
 
 bool SelectionDAG::isKnownNeverNaN(SDValue Op, bool SNaN, unsigned Depth) const {

llvm/test/CodeGen/AVR/base-with-add-like-constant-offset.ll

@@ -0,0 +1,18 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=avr %s -start-before=avr-isel -o - | FileCheck %s
+
+define void @test(i16 %x, ptr addrspace(1) %o) {
+; CHECK-LABEL: test:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    mov r30, r22
+; CHECK-NEXT:    mov r31, r23
+; CHECK-NEXT:    std Z+11, r25
+; CHECK-NEXT:    std Z+10, r24
+; CHECK-NEXT:    ret
+  %int = ptrtoint ptr addrspace(1) %o to i16
+  %or = or disjoint i16 %int, 10
+  %addr = inttoptr i16 %or to ptr addrspace(1)
+  store i16 %x, ptr addrspace(1) %addr
+  ret void
+}
+