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labrinealabrinea
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[FMV][AArch64] Remove features which expose non exploitable runtime behavior.
Features dit, ebf16, memtag3, and rpres allow existing instructions to behave differently depending on the value of certain control registers. FMV does not read the content of control registers making these features unsuitable for runtime dispatch. See the ACLE patch for more info: ARM-software/acle#355
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13 files changed

+55
-82
lines changed

13 files changed

+55
-82
lines changed

‎clang/test/CodeGen/aarch64-cpu-supports-target.c‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -5,19 +5,19 @@ int check_all_feature() {
55
return 1;
66
else if (__builtin_cpu_supports("rdm+lse+fp+simd+crc+sha1+sha2+sha3"))
77
return 2;
8-
else if (__builtin_cpu_supports("aes+pmull+fp16+dit+dpb+dpb2+jscvt"))
8+
else if (__builtin_cpu_supports("aes+pmull+fp16+dpb+dpb2+jscvt"))
99
return 3;
1010
else if (__builtin_cpu_supports("fcma+rcpc+rcpc2+rcpc3+frintts+dgh"))
1111
return 4;
12-
else if (__builtin_cpu_supports("i8mm+bf16+ebf16+rpres+sve"))
12+
else if (__builtin_cpu_supports("i8mm+bf16+sve"))
1313
return 5;
1414
else if (__builtin_cpu_supports("sve+ebf16+i8mm+f32mm+f64mm"))
1515
return 6;
1616
else if (__builtin_cpu_supports("sve2+sve2-aes+sve2-pmull128"))
1717
return 7;
1818
else if (__builtin_cpu_supports("sve2-bitperm+sve2-sha3+sve2-sm4"))
1919
return 8;
20-
else if (__builtin_cpu_supports("sme+memtag+memtag3+sb"))
20+
else if (__builtin_cpu_supports("sme+memtag+sb"))
2121
return 9;
2222
else if (__builtin_cpu_supports("predres+ssbs+ssbs2+bti+ls64+ls64_v"))
2323
return 10;

‎clang/test/CodeGen/aarch64-fmv-dependencies.c‎

Lines changed: 2 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@
66
// CHECK: define dso_local i32 @fmv._Maes() #[[aes:[0-9]+]] {
77
__attribute__((target_version("aes"))) int fmv(void) { return 0; }
88

9-
// CHECK: define dso_local i32 @fmv._Mbf16() #[[bf16_ebf16:[0-9]+]] {
9+
// CHECK: define dso_local i32 @fmv._Mbf16() #[[bf16:[0-9]+]] {
1010
__attribute__((target_version("bf16"))) int fmv(void) { return 0; }
1111

1212
// CHECK: define dso_local i32 @fmv._Mbti() #[[bti:[0-9]+]] {
@@ -18,9 +18,6 @@ __attribute__((target_version("crc"))) int fmv(void) { return 0; }
1818
// CHECK: define dso_local i32 @fmv._Mdgh() #[[ATTR0:[0-9]+]] {
1919
__attribute__((target_version("dgh"))) int fmv(void) { return 0; }
2020

21-
// CHECK: define dso_local i32 @fmv._Mdit() #[[dit:[0-9]+]] {
22-
__attribute__((target_version("dit"))) int fmv(void) { return 0; }
23-
2421
// CHECK: define dso_local i32 @fmv._Mdotprod() #[[dotprod:[0-9]+]] {
2522
__attribute__((target_version("dotprod"))) int fmv(void) { return 0; }
2623

@@ -30,9 +27,6 @@ __attribute__((target_version("dpb"))) int fmv(void) { return 0; }
3027
// CHECK: define dso_local i32 @fmv._Mdpb2() #[[dpb2:[0-9]+]] {
3128
__attribute__((target_version("dpb2"))) int fmv(void) { return 0; }
3229

33-
// CHECK: define dso_local i32 @fmv._Mebf16() #[[bf16_ebf16:[0-9]+]] {
34-
__attribute__((target_version("ebf16"))) int fmv(void) { return 0; }
35-
3630
// CHECK: define dso_local i32 @fmv._Mf32mm() #[[f32mm:[0-9]+]] {
3731
__attribute__((target_version("f32mm"))) int fmv(void) { return 0; }
3832

@@ -75,9 +69,6 @@ __attribute__((target_version("lse"))) int fmv(void) { return 0; }
7569
// CHECK: define dso_local i32 @fmv._Mmemtag() #[[memtag:[0-9]+]] {
7670
__attribute__((target_version("memtag"))) int fmv(void) { return 0; }
7771

78-
// CHECK: define dso_local i32 @fmv._Mmemtag3() #[[memtag:[0-9]+]] {
79-
__attribute__((target_version("memtag3"))) int fmv(void) { return 0; }
80-
8172
// CHECK: define dso_local i32 @fmv._Mmops() #[[mops:[0-9]+]] {
8273
__attribute__((target_version("mops"))) int fmv(void) { return 0; }
8374

@@ -99,9 +90,6 @@ __attribute__((target_version("rdm"))) int fmv(void) { return 0; }
9990
// CHECK: define dso_local i32 @fmv._Mrng() #[[rng:[0-9]+]] {
10091
__attribute__((target_version("rng"))) int fmv(void) { return 0; }
10192

102-
// CHECK: define dso_local i32 @fmv._Mrpres() #[[ATTR0:[0-9]+]] {
103-
__attribute__((target_version("rpres"))) int fmv(void) { return 0; }
104-
10593
// CHECK: define dso_local i32 @fmv._Msb() #[[sb:[0-9]+]] {
10694
__attribute__((target_version("sb"))) int fmv(void) { return 0; }
10795

@@ -163,11 +151,10 @@ int caller() {
163151
}
164152

165153
// CHECK: attributes #[[aes]] = { {{.*}} "target-features"="+aes,+fp-armv8,+neon,+outline-atomics,+v8a"
166-
// CHECK: attributes #[[bf16_ebf16]] = { {{.*}} "target-features"="+bf16,+fp-armv8,+neon,+outline-atomics,+v8a"
154+
// CHECK: attributes #[[bf16]] = { {{.*}} "target-features"="+bf16,+fp-armv8,+neon,+outline-atomics,+v8a"
167155
// CHECK: attributes #[[bti]] = { {{.*}} "target-features"="+bti,+fp-armv8,+neon,+outline-atomics,+v8a"
168156
// CHECK: attributes #[[crc]] = { {{.*}} "target-features"="+crc,+fp-armv8,+neon,+outline-atomics,+v8a"
169157
// CHECK: attributes #[[ATTR0]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+v8a"
170-
// CHECK: attributes #[[dit]] = { {{.*}} "target-features"="+dit,+fp-armv8,+neon,+outline-atomics,+v8a"
171158
// CHECK: attributes #[[dotprod]] = { {{.*}} "target-features"="+dotprod,+fp-armv8,+neon,+outline-atomics,+v8a"
172159
// CHECK: attributes #[[dpb]] = { {{.*}} "target-features"="+ccpp,+fp-armv8,+neon,+outline-atomics,+v8a"
173160
// CHECK: attributes #[[dpb2]] = { {{.*}} "target-features"="+ccdp,+ccpp,+fp-armv8,+neon,+outline-atomics,+v8a"

‎clang/test/CodeGen/attr-target-version.c‎

Lines changed: 31 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -27,15 +27,15 @@ int foo() {
2727
inline int __attribute__((target_version("sha2+aes+f64mm"))) fmv_inline(void) { return 1; }
2828
inline int __attribute__((target_version("fp16+fcma+rdma+sme+ fp16 "))) fmv_inline(void) { return 2; }
2929
inline int __attribute__((target_version("sha3+i8mm+f32mm"))) fmv_inline(void) { return 12; }
30-
inline int __attribute__((target_version("dit+ebf16"))) fmv_inline(void) { return 8; }
30+
inline int __attribute__((target_version("bf16"))) fmv_inline(void) { return 8; }
3131
inline int __attribute__((target_version("dpb+rcpc2 "))) fmv_inline(void) { return 6; }
3232
inline int __attribute__((target_version(" dpb2 + jscvt"))) fmv_inline(void) { return 7; }
3333
inline int __attribute__((target_version("rcpc+frintts"))) fmv_inline(void) { return 3; }
3434
inline int __attribute__((target_version("sve+bf16"))) fmv_inline(void) { return 4; }
3535
inline int __attribute__((target_version("sve2-aes+sve2-sha3"))) fmv_inline(void) { return 5; }
3636
inline int __attribute__((target_version("sve2+sve2-aes+sve2-bitperm"))) fmv_inline(void) { return 9; }
3737
inline int __attribute__((target_version("sve2-sm4+memtag"))) fmv_inline(void) { return 10; }
38-
inline int __attribute__((target_version("memtag3+rcpc3+mops"))) fmv_inline(void) { return 11; }
38+
inline int __attribute__((target_version("memtag+rcpc3+mops"))) fmv_inline(void) { return 11; }
3939
inline int __attribute__((target_version("aes+dotprod"))) fmv_inline(void) { return 13; }
4040
inline int __attribute__((target_version("simd+fp16fml"))) fmv_inline(void) { return 14; }
4141
inline int __attribute__((target_version("fp+sm4"))) fmv_inline(void) { return 15; }
@@ -680,7 +680,7 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
680680
//
681681
//
682682
// CHECK: Function Attrs: noinline nounwind optnone
683-
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MditMebf16
683+
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mbf16
684684
// CHECK-SAME: () #[[ATTR28:[0-9]+]] {
685685
// CHECK-NEXT: entry:
686686
// CHECK-NEXT: ret i32 8
@@ -736,7 +736,7 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
736736
//
737737
//
738738
// CHECK: Function Attrs: noinline nounwind optnone
739-
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mmemtag3MmopsMrcpc3
739+
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MmemtagMmopsMrcpc3
740740
// CHECK-SAME: () #[[ATTR36:[0-9]+]] {
741741
// CHECK-NEXT: entry:
742742
// CHECK-NEXT: ret i32 11
@@ -789,12 +789,12 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
789789
// CHECK-NEXT: ret ptr @fmv_inline._MfcmaMfp16MrdmMsme
790790
// CHECK: resolver_else:
791791
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
792-
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 864726312827224064
793-
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 864726312827224064
792+
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 864708720641179648
793+
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 864708720641179648
794794
// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
795795
// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
796796
// CHECK: resolver_return1:
797-
// CHECK-NEXT: ret ptr @fmv_inline._Mmemtag3MmopsMrcpc3
797+
// CHECK-NEXT: ret ptr @fmv_inline._MmemtagMmopsMrcpc3
798798
// CHECK: resolver_else2:
799799
// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
800800
// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 893353197568
@@ -845,68 +845,68 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
845845
// CHECK-NEXT: ret ptr @fmv_inline._Mbf16Msve
846846
// CHECK: resolver_else14:
847847
// CHECK-NEXT: [[TMP32:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
848-
// CHECK-NEXT: [[TMP33:%.*]] = and i64 [[TMP32]], 268566528
849-
// CHECK-NEXT: [[TMP34:%.*]] = icmp eq i64 [[TMP33]], 268566528
848+
// CHECK-NEXT: [[TMP33:%.*]] = and i64 [[TMP32]], 20971520
849+
// CHECK-NEXT: [[TMP34:%.*]] = icmp eq i64 [[TMP33]], 20971520
850850
// CHECK-NEXT: [[TMP35:%.*]] = and i1 true, [[TMP34]]
851851
// CHECK-NEXT: br i1 [[TMP35]], label [[RESOLVER_RETURN15:%.*]], label [[RESOLVER_ELSE16:%.*]]
852852
// CHECK: resolver_return15:
853-
// CHECK-NEXT: ret ptr @fmv_inline._MditMebf16
853+
// CHECK-NEXT: ret ptr @fmv_inline._MfrinttsMrcpc
854854
// CHECK: resolver_else16:
855855
// CHECK-NEXT: [[TMP36:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
856-
// CHECK-NEXT: [[TMP37:%.*]] = and i64 [[TMP36]], 20971520
857-
// CHECK-NEXT: [[TMP38:%.*]] = icmp eq i64 [[TMP37]], 20971520
856+
// CHECK-NEXT: [[TMP37:%.*]] = and i64 [[TMP36]], 8650752
857+
// CHECK-NEXT: [[TMP38:%.*]] = icmp eq i64 [[TMP37]], 8650752
858858
// CHECK-NEXT: [[TMP39:%.*]] = and i1 true, [[TMP38]]
859859
// CHECK-NEXT: br i1 [[TMP39]], label [[RESOLVER_RETURN17:%.*]], label [[RESOLVER_ELSE18:%.*]]
860860
// CHECK: resolver_return17:
861-
// CHECK-NEXT: ret ptr @fmv_inline._MfrinttsMrcpc
861+
// CHECK-NEXT: ret ptr @fmv_inline._MdpbMrcpc2
862862
// CHECK: resolver_else18:
863863
// CHECK-NEXT: [[TMP40:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
864-
// CHECK-NEXT: [[TMP41:%.*]] = and i64 [[TMP40]], 8650752
865-
// CHECK-NEXT: [[TMP42:%.*]] = icmp eq i64 [[TMP41]], 8650752
864+
// CHECK-NEXT: [[TMP41:%.*]] = and i64 [[TMP40]], 1572864
865+
// CHECK-NEXT: [[TMP42:%.*]] = icmp eq i64 [[TMP41]], 1572864
866866
// CHECK-NEXT: [[TMP43:%.*]] = and i1 true, [[TMP42]]
867867
// CHECK-NEXT: br i1 [[TMP43]], label [[RESOLVER_RETURN19:%.*]], label [[RESOLVER_ELSE20:%.*]]
868868
// CHECK: resolver_return19:
869-
// CHECK-NEXT: ret ptr @fmv_inline._MdpbMrcpc2
869+
// CHECK-NEXT: ret ptr @fmv_inline._Mdpb2Mjscvt
870870
// CHECK: resolver_else20:
871871
// CHECK-NEXT: [[TMP44:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
872-
// CHECK-NEXT: [[TMP45:%.*]] = and i64 [[TMP44]], 1572864
873-
// CHECK-NEXT: [[TMP46:%.*]] = icmp eq i64 [[TMP45]], 1572864
872+
// CHECK-NEXT: [[TMP45:%.*]] = and i64 [[TMP44]], 520
873+
// CHECK-NEXT: [[TMP46:%.*]] = icmp eq i64 [[TMP45]], 520
874874
// CHECK-NEXT: [[TMP47:%.*]] = and i1 true, [[TMP46]]
875875
// CHECK-NEXT: br i1 [[TMP47]], label [[RESOLVER_RETURN21:%.*]], label [[RESOLVER_ELSE22:%.*]]
876876
// CHECK: resolver_return21:
877-
// CHECK-NEXT: ret ptr @fmv_inline._Mdpb2Mjscvt
877+
// CHECK-NEXT: ret ptr @fmv_inline._Mfp16fmlMsimd
878878
// CHECK: resolver_else22:
879879
// CHECK-NEXT: [[TMP48:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
880-
// CHECK-NEXT: [[TMP49:%.*]] = and i64 [[TMP48]], 520
881-
// CHECK-NEXT: [[TMP50:%.*]] = icmp eq i64 [[TMP49]], 520
880+
// CHECK-NEXT: [[TMP49:%.*]] = and i64 [[TMP48]], 32784
881+
// CHECK-NEXT: [[TMP50:%.*]] = icmp eq i64 [[TMP49]], 32784
882882
// CHECK-NEXT: [[TMP51:%.*]] = and i1 true, [[TMP50]]
883883
// CHECK-NEXT: br i1 [[TMP51]], label [[RESOLVER_RETURN23:%.*]], label [[RESOLVER_ELSE24:%.*]]
884884
// CHECK: resolver_return23:
885-
// CHECK-NEXT: ret ptr @fmv_inline._Mfp16fmlMsimd
885+
// CHECK-NEXT: ret ptr @fmv_inline._MaesMdotprod
886886
// CHECK: resolver_else24:
887887
// CHECK-NEXT: [[TMP52:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
888-
// CHECK-NEXT: [[TMP53:%.*]] = and i64 [[TMP52]], 32784
889-
// CHECK-NEXT: [[TMP54:%.*]] = icmp eq i64 [[TMP53]], 32784
888+
// CHECK-NEXT: [[TMP53:%.*]] = and i64 [[TMP52]], 192
889+
// CHECK-NEXT: [[TMP54:%.*]] = icmp eq i64 [[TMP53]], 192
890890
// CHECK-NEXT: [[TMP55:%.*]] = and i1 true, [[TMP54]]
891891
// CHECK-NEXT: br i1 [[TMP55]], label [[RESOLVER_RETURN25:%.*]], label [[RESOLVER_ELSE26:%.*]]
892892
// CHECK: resolver_return25:
893-
// CHECK-NEXT: ret ptr @fmv_inline._MaesMdotprod
893+
// CHECK-NEXT: ret ptr @fmv_inline._MlseMrdm
894894
// CHECK: resolver_else26:
895895
// CHECK-NEXT: [[TMP56:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
896-
// CHECK-NEXT: [[TMP57:%.*]] = and i64 [[TMP56]], 192
897-
// CHECK-NEXT: [[TMP58:%.*]] = icmp eq i64 [[TMP57]], 192
896+
// CHECK-NEXT: [[TMP57:%.*]] = and i64 [[TMP56]], 288
897+
// CHECK-NEXT: [[TMP58:%.*]] = icmp eq i64 [[TMP57]], 288
898898
// CHECK-NEXT: [[TMP59:%.*]] = and i1 true, [[TMP58]]
899899
// CHECK-NEXT: br i1 [[TMP59]], label [[RESOLVER_RETURN27:%.*]], label [[RESOLVER_ELSE28:%.*]]
900900
// CHECK: resolver_return27:
901-
// CHECK-NEXT: ret ptr @fmv_inline._MlseMrdm
901+
// CHECK-NEXT: ret ptr @fmv_inline._MfpMsm4
902902
// CHECK: resolver_else28:
903903
// CHECK-NEXT: [[TMP60:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
904-
// CHECK-NEXT: [[TMP61:%.*]] = and i64 [[TMP60]], 288
905-
// CHECK-NEXT: [[TMP62:%.*]] = icmp eq i64 [[TMP61]], 288
904+
// CHECK-NEXT: [[TMP61:%.*]] = and i64 [[TMP60]], 134217728
905+
// CHECK-NEXT: [[TMP62:%.*]] = icmp eq i64 [[TMP61]], 134217728
906906
// CHECK-NEXT: [[TMP63:%.*]] = and i1 true, [[TMP62]]
907907
// CHECK-NEXT: br i1 [[TMP63]], label [[RESOLVER_RETURN29:%.*]], label [[RESOLVER_ELSE30:%.*]]
908908
// CHECK: resolver_return29:
909-
// CHECK-NEXT: ret ptr @fmv_inline._MfpMsm4
909+
// CHECK-NEXT: ret ptr @fmv_inline._Mbf16
910910
// CHECK: resolver_else30:
911911
// CHECK-NEXT: ret ptr @fmv_inline.default
912912
//

‎clang/test/CodeGenCXX/attr-target-version.cpp‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33

44
int __attribute__((target_version("sme-f64f64+bf16"))) foo(int) { return 1; }
55
int __attribute__((target_version("default"))) foo(int) { return 2; }
6-
int __attribute__((target_version("sm4+ebf16"))) foo(void) { return 3; }
6+
int __attribute__((target_version("sm4+bf16"))) foo(void) { return 3; }
77
int __attribute__((target_version("default"))) foo(void) { return 4; }
88

99
struct MyClass {
@@ -84,7 +84,7 @@ int bar() {
8484
// CHECK-NEXT: ret i32 2
8585
//
8686
//
87-
// CHECK-LABEL: define dso_local noundef i32 @_Z3foov._Mebf16Msm4(
87+
// CHECK-LABEL: define dso_local noundef i32 @_Z3foov._Mbf16Msm4(
8888
// CHECK-SAME: ) #[[ATTR2:[0-9]+]] {
8989
// CHECK-NEXT: [[ENTRY:.*:]]
9090
// CHECK-NEXT: ret i32 3
@@ -249,12 +249,12 @@ int bar() {
249249
// CHECK-NEXT: [[RESOLVER_ENTRY:.*:]]
250250
// CHECK-NEXT: call void @__init_cpu_features_resolver()
251251
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
252-
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 268435488
253-
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 268435488
252+
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 134217760
253+
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 134217760
254254
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
255255
// CHECK-NEXT: br i1 [[TMP3]], label %[[RESOLVER_RETURN:.*]], label %[[RESOLVER_ELSE:.*]]
256256
// CHECK: [[RESOLVER_RETURN]]:
257-
// CHECK-NEXT: ret ptr @_Z3foov._Mebf16Msm4
257+
// CHECK-NEXT: ret ptr @_Z3foov._Mbf16Msm4
258258
// CHECK: [[RESOLVER_ELSE]]:
259259
// CHECK-NEXT: ret ptr @_Z3foov.default
260260
//

‎clang/test/Sema/aarch64-cpu-supports.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@ int test_aarch64_features(void) {
1212
if (__builtin_cpu_supports("pmull128"))
1313
return 3;
1414
// expected-warning@+1 {{invalid cpu feature string}}
15-
if (__builtin_cpu_supports("sve2,rpres"))
15+
if (__builtin_cpu_supports("sve2,sve"))
1616
return 4;
1717
// expected-warning@+1 {{invalid cpu feature string}}
1818
if (__builtin_cpu_supports("dgh+sve2-pmull"))

‎clang/test/Sema/attr-target-clones-aarch64.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@ int __attribute__((target_clones("rng", "fp16fml+fp", "default"))) redecl4(void)
2222
// expected-error@+3 {{'target_clones' attribute does not match previous declaration}}
2323
// expected-note@-2 {{previous declaration is here}}
2424
// expected-warning@+1 {{version list contains entries that don't impact code generation}}
25-
int __attribute__((target_clones("dgh+rpres", "ebf16+dpb", "default"))) redecl4(void) { return 1; }
25+
int __attribute__((target_clones("dgh", "bf16+dpb", "default"))) redecl4(void) { return 1; }
2626

2727
int __attribute__((target_version("flagm2"))) redef2(void) { return 1; }
2828
// expected-error@+2 {{multiversioned function redeclarations require identical target attributes}}
@@ -69,7 +69,7 @@ empty_target_5(void);
6969
void __attribute__((target_clones("sve2-bitperm", "sve2-bitperm")))
7070
dupe_normal(void);
7171

72-
void __attribute__((target_clones("default"), target_clones("memtag3+bti"))) dupe_normal2(void);
72+
void __attribute__((target_clones("default"), target_clones("memtag+bti"))) dupe_normal2(void);
7373

7474
int mv_after_use(void);
7575
int useage(void) {

‎clang/test/Sema/attr-target-version.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -44,7 +44,7 @@ int __attribute__((target_version("lse"))) main(void) { return 1; }
4444

4545
// It is ok for the default version to appear first.
4646
int default_first(void) { return 1; }
47-
int __attribute__((target_version("dit"))) default_first(void) { return 2; }
47+
int __attribute__((target_version("lse"))) default_first(void) { return 2; }
4848
int __attribute__((target_version("mops"))) default_first(void) { return 3; }
4949

5050
// It is ok if the default version is between other versions.
@@ -77,7 +77,7 @@ void __attribute__((target_version("rdm+rng+crc"))) redef(void) {}
7777
void __attribute__((target_version("rdm+rng+crc"))) redef(void) {}
7878

7979
int def(void);
80-
void __attribute__((target_version("dit"))) nodef(void);
80+
void __attribute__((target_version("lse"))) nodef(void);
8181
void __attribute__((target_version("ls64"))) nodef(void);
8282
void __attribute__((target_version("aes"))) ovl(void);
8383
void __attribute__((target_version("default"))) ovl(void);

‎clang/test/SemaCXX/attr-target-version.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@ int __attribute__((target_version("flagm2"))) diff_link2(void) { return 1; }
3131
extern int __attribute__((target_version("flagm"))) diff_link2(void);
3232

3333
namespace {
34-
static int __attribute__((target_version("memtag3"))) diff_link2(void) { return 2; }
34+
static int __attribute__((target_version("memtag"))) diff_link2(void) { return 2; }
3535
int __attribute__((target_version("sve2-bitperm"))) diff_link2(void) { return 1; }
3636
} // namespace
3737

‎compiler-rt/lib/builtins/cpu_model/AArch64CPUFeatures.inc‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,7 @@ enum CPUFeatures {
3939
RESERVED_FEAT_AES, // previously used and now ABI legacy
4040
FEAT_PMULL,
4141
FEAT_FP16,
42-
FEAT_DIT,
42+
RESERVED_FEAT_DIT, // previously used and now ABI legacy
4343
FEAT_DPB,
4444
FEAT_DPB2,
4545
FEAT_JSCVT,
@@ -50,8 +50,8 @@ enum CPUFeatures {
5050
FEAT_DGH,
5151
FEAT_I8MM,
5252
FEAT_BF16,
53-
FEAT_EBF16,
54-
FEAT_RPRES,
53+
RESERVED_FEAT_EBF16, // previously used and now ABI legacy
54+
RESERVED_FEAT_RPRES, // previously used and now ABI legacy
5555
FEAT_SVE,
5656
RESERVED_FEAT_SVE_BF16, // previously used and now ABI legacy
5757
RESERVED_FEAT_SVE_EBF16, // previously used and now ABI legacy
@@ -67,7 +67,7 @@ enum CPUFeatures {
6767
FEAT_SME,
6868
RESERVED_FEAT_MEMTAG, // previously used and now ABI legacy
6969
FEAT_MEMTAG2,
70-
FEAT_MEMTAG3,
70+
RESERVED_FEAT_MEMTAG3, // previously used and now ABI legacy
7171
FEAT_SB,
7272
FEAT_PREDRES,
7373
RESERVED_FEAT_SSBS, // previously used and now ABI legacy

‎compiler-rt/lib/builtins/cpu_model/aarch64/fmv/apple.inc‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -85,7 +85,6 @@ void __init_cpu_features_resolver(void) {
8585
CHECK_BIT(CAP_BIT_FEAT_DPB2, FEAT_DPB2);
8686
CHECK_BIT(CAP_BIT_FEAT_BF16, FEAT_BF16);
8787
CHECK_BIT(CAP_BIT_FEAT_I8MM, FEAT_I8MM);
88-
CHECK_BIT(CAP_BIT_FEAT_DIT, FEAT_DIT);
8988
CHECK_BIT(CAP_BIT_FEAT_FP16, FEAT_FP16);
9089
CHECK_BIT(CAP_BIT_FEAT_SSBS, FEAT_SSBS2);
9190
CHECK_BIT(CAP_BIT_FEAT_BTI, FEAT_BTI);
@@ -121,7 +120,6 @@ void __init_cpu_features_resolver(void) {
121120
{"hw.optional.arm.FEAT_SHA3", FEAT_SHA3},
122121
{"hw.optional.arm.FEAT_PMULL", FEAT_PMULL},
123122
{"hw.optional.arm.FEAT_FP16", FEAT_FP16},
124-
{"hw.optional.arm.FEAT_DIT", FEAT_DIT},
125123
{"hw.optional.arm.FEAT_DPB", FEAT_DPB},
126124
{"hw.optional.arm.FEAT_DPB2", FEAT_DPB2},
127125
{"hw.optional.arm.FEAT_JSCVT", FEAT_JSCVT},

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