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Thorsten Schütt
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[GlobalIsel] Combine zext of trunc (episode II)
The One with the Sonogram at the End Either replace zext(trunc(x)) with x or If we're actually extending zero bits, then if SrcSize < DstSize: zext(a & mask) SrcSize == DstSize: a & mask SrcSize > DstSize: trunc(a) & mask Credits: https://reviews.llvm.org/D96031 InstCombinerImpl::visitZExt LegalizationArtifactCombiner::tryCombineZExt Test: AMDGPU/GlobalISel/combine-zext-trunc.mir
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‎llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -388,9 +388,6 @@ class CombinerHelper {
388388
/// Transform anyext(trunc(x)) to x.
389389
bool matchCombineAnyExtTrunc(MachineInstr &MI, Register &Reg);
390390

391-
/// Transform zext(trunc(x)) to x.
392-
bool matchCombineZextTrunc(MachineInstr &MI, Register &Reg);
393-
394391
/// Transform trunc (shl x, K) to shl (trunc x), K
395392
/// if K < VT.getScalarSizeInBits().
396393
///
@@ -918,6 +915,10 @@ class CombinerHelper {
918915
bool matchCanonicalizeICmp(const MachineInstr &MI, BuildFnTy &MatchInfo);
919916
bool matchCanonicalizeFCmp(const MachineInstr &MI, BuildFnTy &MatchInfo);
920917

918+
/// Transform zext of truncate to x or and(x, mask).
919+
bool matchCombineZextTrunc(const MachineInstr &ZextMI,
920+
const MachineInstr &TruncMI, BuildFnTy &MatchInfo);
921+
921922
private:
922923
/// Checks for legality of an indexed variant of \p LdSt.
923924
bool isIndexedLoadStoreLegal(GLoadStore &LdSt) const;

‎llvm/include/llvm/Target/GlobalISel/Combine.td‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -758,15 +758,6 @@ def anyext_trunc_fold: GICombineRule <
758758
(apply [{ Helper.replaceSingleDefInstWithReg(*${root}, ${matchinfo}); }])
759759
>;
760760

761-
// Fold (zext (trunc x)) -> x if the source type is same as the destination type
762-
// and truncated bits are known to be zero.
763-
def zext_trunc_fold: GICombineRule <
764-
(defs root:$root, register_matchinfo:$matchinfo),
765-
(match (wip_match_opcode G_ZEXT):$root,
766-
[{ return Helper.matchCombineZextTrunc(*${root}, ${matchinfo}); }]),
767-
(apply [{ Helper.replaceSingleDefInstWithReg(*${root}, ${matchinfo}); }])
768-
>;
769-
770761
def not_cmp_fold_matchinfo : GIDefMatchData<"SmallVector<Register, 4>">;
771762
def not_cmp_fold : GICombineRule<
772763
(defs root:$d, not_cmp_fold_matchinfo:$info),
@@ -1791,6 +1782,15 @@ class integer_of_opcode<Instruction castOpcode> : GICombineRule <
17911782

17921783
def integer_of_truncate : integer_of_opcode<G_TRUNC>;
17931784

1785+
/// Transform zext of truncate to x or and(x, mask).
1786+
def zext_of_truncate : GICombineRule <
1787+
(defs root:$root, build_fn_matchinfo:$matchinfo),
1788+
(match (G_TRUNC $trunc, $src):$TruncMI,
1789+
(G_ZEXT $root, $trunc):$ZextMI,
1790+
[{ return Helper.matchCombineZextTrunc(*${ZextMI}, *${TruncMI}, ${matchinfo}); }]),
1791+
(apply [{ Helper.applyBuildFn(*${ZextMI}, ${matchinfo}); }])>;
1792+
1793+
17941794
def cast_combines: GICombineGroup<[
17951795
truncate_of_zext,
17961796
truncate_of_sext,
@@ -1812,7 +1812,8 @@ def cast_combines: GICombineGroup<[
18121812
narrow_binop_and,
18131813
narrow_binop_or,
18141814
narrow_binop_xor,
1815-
integer_of_truncate
1815+
integer_of_truncate,
1816+
zext_of_truncate
18161817
]>;
18171818

18181819
def canonicalize_icmp : GICombineRule<
@@ -1869,7 +1870,6 @@ def const_combines : GICombineGroup<[constant_fold_fp_ops, const_ptradd_to_i2p,
18691870

18701871
def known_bits_simplifications : GICombineGroup<[
18711872
redundant_and, redundant_sext_inreg, redundant_or, urem_pow2_to_mask,
1872-
zext_trunc_fold,
18731873
sext_inreg_to_zext_inreg]>;
18741874

18751875
def width_reduction_combines : GICombineGroup<[reduce_shl_of_extend,

‎llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -333,8 +333,10 @@ MachineInstrBuilder CSEMIRBuilder::buildConstant(const DstOp &Res,
333333

334334
// For vectors, CSE the element only for now.
335335
LLT Ty = Res.getLLTTy(*getMRI());
336-
if (Ty.isVector())
336+
if (Ty.isFixedVector())
337337
return buildSplatBuildVector(Res, buildConstant(Ty.getElementType(), Val));
338+
if (Ty.isScalableVector())
339+
return buildSplatVector(Res, buildConstant(Ty.getElementType(), Val));
338340

339341
FoldingSetNodeID ID;
340342
GISelInstProfileBuilder ProfBuilder(ID, *getMRI());

‎llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp‎

Lines changed: 0 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -2526,20 +2526,6 @@ bool CombinerHelper::matchCombineAnyExtTrunc(MachineInstr &MI, Register &Reg) {
25262526
m_GTrunc(m_all_of(m_Reg(Reg), m_SpecificType(DstTy))));
25272527
}
25282528

2529-
bool CombinerHelper::matchCombineZextTrunc(MachineInstr &MI, Register &Reg) {
2530-
assert(MI.getOpcode() == TargetOpcode::G_ZEXT && "Expected a G_ZEXT");
2531-
Register DstReg = MI.getOperand(0).getReg();
2532-
Register SrcReg = MI.getOperand(1).getReg();
2533-
LLT DstTy = MRI.getType(DstReg);
2534-
if (mi_match(SrcReg, MRI,
2535-
m_GTrunc(m_all_of(m_Reg(Reg), m_SpecificType(DstTy))))) {
2536-
unsigned DstSize = DstTy.getScalarSizeInBits();
2537-
unsigned SrcSize = MRI.getType(SrcReg).getScalarSizeInBits();
2538-
return KB->getKnownBits(Reg).countMinLeadingZeros() >= DstSize - SrcSize;
2539-
}
2540-
return false;
2541-
}
2542-
25432529
static LLT getMidVTForTruncRightShiftCombine(LLT ShiftTy, LLT TruncTy) {
25442530
const unsigned ShiftSize = ShiftTy.getScalarSizeInBits();
25452531
const unsigned TruncSize = TruncTy.getScalarSizeInBits();

‎llvm/lib/CodeGen/GlobalISel/CombinerHelperCasts.cpp‎

Lines changed: 91 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -359,3 +359,94 @@ bool CombinerHelper::matchCastOfInteger(const MachineInstr &CastMI,
359359
return false;
360360
}
361361
}
362+
363+
bool CombinerHelper::matchCombineZextTrunc(const MachineInstr &ZextMI,
364+
const MachineInstr &TruncMI,
365+
BuildFnTy &MatchInfo) {
366+
const GZext *Zext = cast<GZext>(&ZextMI);
367+
const GTrunc *Trunc = cast<GTrunc>(&TruncMI);
368+
369+
Register Dst = Zext->getReg(0);
370+
Register Mid = Zext->getSrcReg();
371+
Register Src = Trunc->getSrcReg();
372+
373+
LLT DstTy = MRI.getType(Dst);
374+
LLT SrcTy = MRI.getType(Src);
375+
376+
if (!MRI.hasOneNonDBGUse(Mid))
377+
return false;
378+
379+
unsigned DstSize = DstTy.getScalarSizeInBits();
380+
unsigned MidSize = MRI.getType(Mid).getScalarSizeInBits();
381+
unsigned SrcSize = SrcTy.getScalarSizeInBits();
382+
383+
// Are the truncated bits known to be zero?
384+
if (DstTy == SrcTy &&
385+
(KB->getKnownBits(Src).countMinLeadingZeros() >= DstSize - MidSize)) {
386+
MatchInfo = [=](MachineIRBuilder &B) { B.buildCopy(Dst, Src); };
387+
return true;
388+
}
389+
390+
// If the sizes are just right we can convert this into a logical
391+
// 'and', which will be much cheaper than the pair of casts.
392+
393+
// If we're actually extending zero bits, then if
394+
// SrcSize < DstSize: zext(Src & mask)
395+
// SrcSize == DstSize: Src & mask
396+
// SrcSize > DstSize: trunc(Src) & mask
397+
398+
if (DstSize == SrcSize) {
399+
// Src & mask.
400+
401+
if (!isLegalOrBeforeLegalizer({TargetOpcode::G_AND, {DstTy}}) ||
402+
!isConstantLegalOrBeforeLegalizer(DstTy))
403+
return false;
404+
405+
// build mask.
406+
APInt AndValue(APInt::getLowBitsSet(SrcSize, MidSize));
407+
408+
MatchInfo = [=](MachineIRBuilder &B) {
409+
auto Mask = B.buildConstant(DstTy, AndValue);
410+
B.buildAnd(Dst, Src, Mask);
411+
};
412+
return true;
413+
}
414+
415+
if (SrcSize < DstSize) {
416+
// zext(Src & mask).
417+
418+
if (!isLegalOrBeforeLegalizer({TargetOpcode::G_AND, {SrcTy}}) ||
419+
!isConstantLegalOrBeforeLegalizer(SrcTy) ||
420+
!isLegalOrBeforeLegalizer({TargetOpcode::G_ZEXT, {DstTy, SrcTy}}))
421+
return false;
422+
423+
APInt AndValue(APInt::getLowBitsSet(SrcSize, MidSize));
424+
425+
MatchInfo = [=](MachineIRBuilder &B) {
426+
auto Mask = B.buildConstant(SrcTy, AndValue);
427+
auto And = B.buildAnd(SrcTy, Src, Mask);
428+
B.buildZExt(Dst, And);
429+
};
430+
return true;
431+
}
432+
433+
if (SrcSize > DstSize) {
434+
// trunc(Src) & mask.
435+
436+
if (!isLegalOrBeforeLegalizer({TargetOpcode::G_AND, {DstTy}}) ||
437+
!isConstantLegalOrBeforeLegalizer(DstTy) ||
438+
!isLegalOrBeforeLegalizer({TargetOpcode::G_TRUNC, {DstTy, SrcTy}}))
439+
return false;
440+
441+
APInt AndValue(APInt::getLowBitsSet(DstSize, MidSize));
442+
443+
MatchInfo = [=](MachineIRBuilder &B) {
444+
auto Mask = B.buildConstant(DstTy, AndValue);
445+
auto Trunc = B.buildTrunc(DstTy, Src);
446+
B.buildAnd(Dst, Trunc, Mask);
447+
};
448+
return true;
449+
}
450+
451+
return false;
452+
}

‎llvm/lib/Target/AMDGPU/AMDGPUCombine.td‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -168,6 +168,6 @@ def AMDGPUPostLegalizerCombiner: GICombiner<
168168
def AMDGPURegBankCombiner : GICombiner<
169169
"AMDGPURegBankCombinerImpl",
170170
[unmerge_merge, unmerge_cst, unmerge_undef,
171-
zext_trunc_fold, int_minmax_to_med3, ptr_add_immed_chain,
171+
int_minmax_to_med3, ptr_add_immed_chain,
172172
fp_minmax_to_clamp, fp_minmax_to_med3, fmed3_intrinsic_to_clamp]> {
173173
}

‎llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll‎

Lines changed: 8 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1938,14 +1938,14 @@ define i8 @atomicrmw_add_i8(ptr %ptr, i8 %rhs) {
19381938
define i8 @atomicrmw_xchg_i8(ptr %ptr, i8 %rhs) {
19391939
; CHECK-NOLSE-O1-LABEL: atomicrmw_xchg_i8:
19401940
; CHECK-NOLSE-O1: ; %bb.0:
1941-
; CHECK-NOLSE-O1-NEXT: ; kill: def $w1 killed $w1 def $x1
1941+
; CHECK-NOLSE-O1-NEXT: mov x8, x0
19421942
; CHECK-NOLSE-O1-NEXT: LBB28_1: ; %atomicrmw.start
19431943
; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
1944-
; CHECK-NOLSE-O1-NEXT: ldxrb w8, [x0]
1945-
; CHECK-NOLSE-O1-NEXT: stxrb w9, w1, [x0]
1944+
; CHECK-NOLSE-O1-NEXT: ldxrb w0, [x8]
1945+
; CHECK-NOLSE-O1-NEXT: stxrb w9, w1, [x8]
19461946
; CHECK-NOLSE-O1-NEXT: cbnz w9, LBB28_1
19471947
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
1948-
; CHECK-NOLSE-O1-NEXT: mov w0, w8
1948+
; CHECK-NOLSE-O1-NEXT: ; kill: def $w0 killed $w0 killed $x0
19491949
; CHECK-NOLSE-O1-NEXT: ret
19501950
;
19511951
; CHECK-OUTLINE-O1-LABEL: atomicrmw_xchg_i8:
@@ -2993,14 +2993,14 @@ define i16 @atomicrmw_add_i16(ptr %ptr, i16 %rhs) {
29932993
define i16 @atomicrmw_xchg_i16(ptr %ptr, i16 %rhs) {
29942994
; CHECK-NOLSE-O1-LABEL: atomicrmw_xchg_i16:
29952995
; CHECK-NOLSE-O1: ; %bb.0:
2996-
; CHECK-NOLSE-O1-NEXT: ; kill: def $w1 killed $w1 def $x1
2996+
; CHECK-NOLSE-O1-NEXT: mov x8, x0
29972997
; CHECK-NOLSE-O1-NEXT: LBB38_1: ; %atomicrmw.start
29982998
; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
2999-
; CHECK-NOLSE-O1-NEXT: ldxrh w8, [x0]
3000-
; CHECK-NOLSE-O1-NEXT: stxrh w9, w1, [x0]
2999+
; CHECK-NOLSE-O1-NEXT: ldxrh w0, [x8]
3000+
; CHECK-NOLSE-O1-NEXT: stxrh w9, w1, [x8]
30013001
; CHECK-NOLSE-O1-NEXT: cbnz w9, LBB38_1
30023002
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
3003-
; CHECK-NOLSE-O1-NEXT: mov w0, w8
3003+
; CHECK-NOLSE-O1-NEXT: ; kill: def $w0 killed $w0 killed $x0
30043004
; CHECK-NOLSE-O1-NEXT: ret
30053005
;
30063006
; CHECK-OUTLINE-O1-LABEL: atomicrmw_xchg_i16:
@@ -5996,7 +5996,6 @@ define { i8, i1 } @cmpxchg_i8(ptr %ptr, i8 %desired, i8 %new) {
59965996
; CHECK-NOLSE-O1-LABEL: cmpxchg_i8:
59975997
; CHECK-NOLSE-O1: ; %bb.0:
59985998
; CHECK-NOLSE-O1-NEXT: mov x8, x0
5999-
; CHECK-NOLSE-O1-NEXT: ; kill: def $w2 killed $w2 def $x2
60005999
; CHECK-NOLSE-O1-NEXT: LBB67_1: ; %cmpxchg.start
60016000
; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
60026001
; CHECK-NOLSE-O1-NEXT: ldxrb w0, [x8]
@@ -6103,7 +6102,6 @@ define { i16, i1 } @cmpxchg_i16(ptr %ptr, i16 %desired, i16 %new) {
61036102
; CHECK-NOLSE-O1-LABEL: cmpxchg_i16:
61046103
; CHECK-NOLSE-O1: ; %bb.0:
61056104
; CHECK-NOLSE-O1-NEXT: mov x8, x0
6106-
; CHECK-NOLSE-O1-NEXT: ; kill: def $w2 killed $w2 def $x2
61076105
; CHECK-NOLSE-O1-NEXT: LBB68_1: ; %cmpxchg.start
61086106
; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
61096107
; CHECK-NOLSE-O1-NEXT: ldxrh w0, [x8]

‎llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll‎

Lines changed: 16 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -746,20 +746,20 @@ define i8 @atomicrmw_xchg_i8(ptr %ptr, i8 %rhs) {
746746
; CHECK-NEXT: successors: %bb.1(0x80000000)
747747
; CHECK-NEXT: liveins: $w1, $x0
748748
; CHECK-NEXT: {{ $}}
749-
; CHECK-NEXT: renamable $w1 = KILL $w1, implicit-def $x1
749+
; CHECK-NEXT: $x8 = ORRXrs $xzr, $x0, 0
750750
; CHECK-NEXT: {{ $}}
751751
; CHECK-NEXT: bb.1.atomicrmw.start:
752752
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
753-
; CHECK-NEXT: liveins: $x0, $x1
753+
; CHECK-NEXT: liveins: $w1, $x8
754754
; CHECK-NEXT: {{ $}}
755-
; CHECK-NEXT: renamable $w8 = LDXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s8) from %ir.ptr)
756-
; CHECK-NEXT: early-clobber renamable $w9 = STXRB renamable $w1, renamable $x0, pcsections !0 :: (volatile store (s8) into %ir.ptr)
755+
; CHECK-NEXT: renamable $w0 = LDXRB renamable $x8, implicit-def $x0, pcsections !0 :: (volatile load (s8) from %ir.ptr)
756+
; CHECK-NEXT: early-clobber renamable $w9 = STXRB renamable $w1, renamable $x8, pcsections !0 :: (volatile store (s8) into %ir.ptr)
757757
; CHECK-NEXT: CBNZW killed renamable $w9, %bb.1, pcsections !0
758758
; CHECK-NEXT: {{ $}}
759759
; CHECK-NEXT: bb.2.atomicrmw.end:
760-
; CHECK-NEXT: liveins: $x8
760+
; CHECK-NEXT: liveins: $x0
761761
; CHECK-NEXT: {{ $}}
762-
; CHECK-NEXT: $w0 = ORRWrs $wzr, $w8, 0, implicit killed $x8
762+
; CHECK-NEXT: $w0 = KILL renamable $w0, implicit killed $x0
763763
; CHECK-NEXT: RET undef $lr, implicit $w0
764764
%res = atomicrmw xchg ptr %ptr, i8 %rhs monotonic, !pcsections !0
765765
ret i8 %res
@@ -999,20 +999,20 @@ define i16 @atomicrmw_xchg_i16(ptr %ptr, i16 %rhs) {
999999
; CHECK-NEXT: successors: %bb.1(0x80000000)
10001000
; CHECK-NEXT: liveins: $w1, $x0
10011001
; CHECK-NEXT: {{ $}}
1002-
; CHECK-NEXT: renamable $w1 = KILL $w1, implicit-def $x1
1002+
; CHECK-NEXT: $x8 = ORRXrs $xzr, $x0, 0
10031003
; CHECK-NEXT: {{ $}}
10041004
; CHECK-NEXT: bb.1.atomicrmw.start:
10051005
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
1006-
; CHECK-NEXT: liveins: $x0, $x1
1006+
; CHECK-NEXT: liveins: $w1, $x8
10071007
; CHECK-NEXT: {{ $}}
1008-
; CHECK-NEXT: renamable $w8 = LDXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s16) from %ir.ptr)
1009-
; CHECK-NEXT: early-clobber renamable $w9 = STXRH renamable $w1, renamable $x0, pcsections !0 :: (volatile store (s16) into %ir.ptr)
1008+
; CHECK-NEXT: renamable $w0 = LDXRH renamable $x8, implicit-def $x0, pcsections !0 :: (volatile load (s16) from %ir.ptr)
1009+
; CHECK-NEXT: early-clobber renamable $w9 = STXRH renamable $w1, renamable $x8, pcsections !0 :: (volatile store (s16) into %ir.ptr)
10101010
; CHECK-NEXT: CBNZW killed renamable $w9, %bb.1, pcsections !0
10111011
; CHECK-NEXT: {{ $}}
10121012
; CHECK-NEXT: bb.2.atomicrmw.end:
1013-
; CHECK-NEXT: liveins: $x8
1013+
; CHECK-NEXT: liveins: $x0
10141014
; CHECK-NEXT: {{ $}}
1015-
; CHECK-NEXT: $w0 = ORRWrs $wzr, $w8, 0, implicit killed $x8
1015+
; CHECK-NEXT: $w0 = KILL renamable $w0, implicit killed $x0
10161016
; CHECK-NEXT: RET undef $lr, implicit $w0
10171017
%res = atomicrmw xchg ptr %ptr, i16 %rhs monotonic, !pcsections !0
10181018
ret i16 %res
@@ -1229,11 +1229,10 @@ define { i8, i1 } @cmpxchg_i8(ptr %ptr, i8 %desired, i8 %new) {
12291229
; CHECK-NEXT: liveins: $w1, $w2, $x0
12301230
; CHECK-NEXT: {{ $}}
12311231
; CHECK-NEXT: $x8 = ORRXrs $xzr, $x0, 0
1232-
; CHECK-NEXT: renamable $w2 = KILL $w2, implicit-def $x2
12331232
; CHECK-NEXT: {{ $}}
12341233
; CHECK-NEXT: bb.1.cmpxchg.start:
12351234
; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.4(0x04000000)
1236-
; CHECK-NEXT: liveins: $w1, $x2, $x8
1235+
; CHECK-NEXT: liveins: $w1, $w2, $x8
12371236
; CHECK-NEXT: {{ $}}
12381237
; CHECK-NEXT: renamable $w0 = LDXRB renamable $x8, implicit-def $x0, pcsections !0 :: (volatile load (s8) from %ir.ptr)
12391238
; CHECK-NEXT: renamable $w9 = ANDWri renamable $w0, 7, pcsections !0
@@ -1242,7 +1241,7 @@ define { i8, i1 } @cmpxchg_i8(ptr %ptr, i8 %desired, i8 %new) {
12421241
; CHECK-NEXT: {{ $}}
12431242
; CHECK-NEXT: bb.2.cmpxchg.trystore:
12441243
; CHECK-NEXT: successors: %bb.3(0x04000000), %bb.1(0x7c000000)
1245-
; CHECK-NEXT: liveins: $w1, $x0, $x2, $x8
1244+
; CHECK-NEXT: liveins: $w1, $w2, $x0, $x8
12461245
; CHECK-NEXT: {{ $}}
12471246
; CHECK-NEXT: early-clobber renamable $w9 = STXRB renamable $w2, renamable $x8, pcsections !0 :: (volatile store (s8) into %ir.ptr)
12481247
; CHECK-NEXT: CBNZW killed renamable $w9, %bb.1
@@ -1272,11 +1271,10 @@ define { i16, i1 } @cmpxchg_i16(ptr %ptr, i16 %desired, i16 %new) {
12721271
; CHECK-NEXT: liveins: $w1, $w2, $x0
12731272
; CHECK-NEXT: {{ $}}
12741273
; CHECK-NEXT: $x8 = ORRXrs $xzr, $x0, 0
1275-
; CHECK-NEXT: renamable $w2 = KILL $w2, implicit-def $x2
12761274
; CHECK-NEXT: {{ $}}
12771275
; CHECK-NEXT: bb.1.cmpxchg.start:
12781276
; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.4(0x04000000)
1279-
; CHECK-NEXT: liveins: $w1, $x2, $x8
1277+
; CHECK-NEXT: liveins: $w1, $w2, $x8
12801278
; CHECK-NEXT: {{ $}}
12811279
; CHECK-NEXT: renamable $w0 = LDXRH renamable $x8, implicit-def $x0, pcsections !0 :: (volatile load (s16) from %ir.ptr)
12821280
; CHECK-NEXT: renamable $w9 = ANDWri renamable $w0, 15, pcsections !0
@@ -1285,7 +1283,7 @@ define { i16, i1 } @cmpxchg_i16(ptr %ptr, i16 %desired, i16 %new) {
12851283
; CHECK-NEXT: {{ $}}
12861284
; CHECK-NEXT: bb.2.cmpxchg.trystore:
12871285
; CHECK-NEXT: successors: %bb.3(0x04000000), %bb.1(0x7c000000)
1288-
; CHECK-NEXT: liveins: $w1, $x0, $x2, $x8
1286+
; CHECK-NEXT: liveins: $w1, $w2, $x0, $x8
12891287
; CHECK-NEXT: {{ $}}
12901288
; CHECK-NEXT: early-clobber renamable $w9 = STXRH renamable $w2, renamable $x8, pcsections !0 :: (volatile store (s16) into %ir.ptr)
12911289
; CHECK-NEXT: CBNZW killed renamable $w9, %bb.1

‎llvm/test/CodeGen/AArch64/GlobalISel/combine-extract-vec-elt.mir‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -49,8 +49,8 @@ body: |
4949
; CHECK: liveins: $x0, $x1
5050
; CHECK-NEXT: {{ $}}
5151
; CHECK-NEXT: %arg1:_(s64) = COPY $x0
52-
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC %arg1(s64)
53-
; CHECK-NEXT: %zext:_(s64) = G_ZEXT [[TRUNC]](s32)
52+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
53+
; CHECK-NEXT: %zext:_(s64) = G_AND %arg1, [[C]]
5454
; CHECK-NEXT: $x0 = COPY %zext(s64)
5555
; CHECK-NEXT: RET_ReallyLR implicit $x0
5656
%arg1:_(s64) = COPY $x0

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