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[RISCV] Preserve MMO when expanding PseudoRV32ZdinxSD/PseudoRV32ZdinxLD.
This allows the asm printer to print the stack spill/reload messages.
1 parent 6295e67 commit 718a229

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2 files changed

+71
-40
lines changed

2 files changed

+71
-40
lines changed

‎llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp‎

Lines changed: 55 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -312,26 +312,40 @@ bool RISCVExpandPseudo::expandRV32ZdinxStore(MachineBasicBlock &MBB,
312312
TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_even);
313313
Register Hi =
314314
TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_odd);
315-
BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
316-
.addReg(Lo, getKillRegState(MBBI->getOperand(0).isKill()))
317-
.addReg(MBBI->getOperand(1).getReg())
318-
.add(MBBI->getOperand(2));
315+
auto MIBLo = BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
316+
.addReg(Lo, getKillRegState(MBBI->getOperand(0).isKill()))
317+
.addReg(MBBI->getOperand(1).getReg())
318+
.add(MBBI->getOperand(2));
319+
320+
MachineMemOperand *MMOHi = nullptr;
321+
if (MBBI->hasOneMemOperand()) {
322+
MachineMemOperand *OldMMO = MBBI->memoperands().front();
323+
MachineFunction *MF = MBB.getParent();
324+
MachineMemOperand *MMOLo = MF->getMachineMemOperand(OldMMO, 0, 4);
325+
MMOHi = MF->getMachineMemOperand(OldMMO, 4, 4);
326+
MIBLo.setMemRefs(MMOLo);
327+
}
328+
319329
if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
320330
// FIXME: Zdinx RV32 can not work on unaligned memory.
321331
assert(!STI->hasFastUnalignedAccess());
322332

323333
assert(MBBI->getOperand(2).getOffset() % 8 == 0);
324334
MBBI->getOperand(2).setOffset(MBBI->getOperand(2).getOffset() + 4);
325-
BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
326-
.addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill()))
327-
.add(MBBI->getOperand(1))
328-
.add(MBBI->getOperand(2));
335+
auto MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
336+
.addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill()))
337+
.add(MBBI->getOperand(1))
338+
.add(MBBI->getOperand(2));
339+
if (MMOHi)
340+
MIBHi.setMemRefs(MMOHi);
329341
} else {
330342
assert(isInt<12>(MBBI->getOperand(2).getImm() + 4));
331-
BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
332-
.addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill()))
333-
.add(MBBI->getOperand(1))
334-
.addImm(MBBI->getOperand(2).getImm() + 4);
343+
auto MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
344+
.addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill()))
345+
.add(MBBI->getOperand(1))
346+
.addImm(MBBI->getOperand(2).getImm() + 4);
347+
if (MMOHi)
348+
MIBHi.setMemRefs(MMOHi);
335349
}
336350
MBBI->eraseFromParent();
337351
return true;
@@ -349,36 +363,53 @@ bool RISCVExpandPseudo::expandRV32ZdinxLoad(MachineBasicBlock &MBB,
349363
Register Hi =
350364
TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_odd);
351365

366+
MachineMemOperand *MMOLo = nullptr;
367+
MachineMemOperand *MMOHi = nullptr;
368+
if (MBBI->hasOneMemOperand()) {
369+
MachineMemOperand *OldMMO = MBBI->memoperands().front();
370+
MachineFunction *MF = MBB.getParent();
371+
MMOLo = MF->getMachineMemOperand(OldMMO, 0, 4);
372+
MMOHi = MF->getMachineMemOperand(OldMMO, 4, 4);
373+
}
374+
352375
// If the register of operand 1 is equal to the Lo register, then swap the
353376
// order of loading the Lo and Hi statements.
354377
bool IsOp1EqualToLo = Lo == MBBI->getOperand(1).getReg();
355378
// Order: Lo, Hi
356379
if (!IsOp1EqualToLo) {
357-
BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo)
358-
.addReg(MBBI->getOperand(1).getReg())
359-
.add(MBBI->getOperand(2));
380+
auto MIBLo = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo)
381+
.addReg(MBBI->getOperand(1).getReg())
382+
.add(MBBI->getOperand(2));
383+
if (MMOLo)
384+
MIBLo.setMemRefs(MMOLo);
360385
}
361386

362387
if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
363388
auto Offset = MBBI->getOperand(2).getOffset();
364389
assert(MBBI->getOperand(2).getOffset() % 8 == 0);
365390
MBBI->getOperand(2).setOffset(Offset + 4);
366-
BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi)
367-
.addReg(MBBI->getOperand(1).getReg())
368-
.add(MBBI->getOperand(2));
391+
auto MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi)
392+
.addReg(MBBI->getOperand(1).getReg())
393+
.add(MBBI->getOperand(2));
369394
MBBI->getOperand(2).setOffset(Offset);
395+
if (MMOHi)
396+
MIBHi.setMemRefs(MMOHi);
370397
} else {
371398
assert(isInt<12>(MBBI->getOperand(2).getImm() + 4));
372-
BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi)
373-
.addReg(MBBI->getOperand(1).getReg())
374-
.addImm(MBBI->getOperand(2).getImm() + 4);
399+
auto MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi)
400+
.addReg(MBBI->getOperand(1).getReg())
401+
.addImm(MBBI->getOperand(2).getImm() + 4);
402+
if (MMOHi)
403+
MIBHi.setMemRefs(MMOHi);
375404
}
376405

377406
// Order: Hi, Lo
378407
if (IsOp1EqualToLo) {
379-
BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo)
380-
.addReg(MBBI->getOperand(1).getReg())
381-
.add(MBBI->getOperand(2));
408+
auto MIBLo = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo)
409+
.addReg(MBBI->getOperand(1).getReg())
410+
.add(MBBI->getOperand(2));
411+
if (MMOLo)
412+
MIBLo.setMemRefs(MMOLo);
382413
}
383414

384415
MBBI->eraseFromParent();

‎llvm/test/CodeGen/RISCV/zdinx-large-spill.mir‎

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -14,28 +14,28 @@
1414
; CHECK-NEXT: .cfi_def_cfa_offset 2064
1515
; CHECK-NEXT: lui t0, 1
1616
; CHECK-NEXT: add t0, sp, t0
17-
; CHECK-NEXT: sw a0, -2040(t0)
18-
; CHECK-NEXT: sw a1, -2036(t0)
17+
; CHECK-NEXT: sw a0, -2040(t0) # 4-byte Folded Spill
18+
; CHECK-NEXT: sw a1, -2036(t0) # 4-byte Folded Spill
1919
; CHECK-NEXT: lui a0, 1
2020
; CHECK-NEXT: add a0, sp, a0
21-
; CHECK-NEXT: sw a2, -2048(a0)
22-
; CHECK-NEXT: sw a3, -2044(a0)
23-
; CHECK-NEXT: sw a4, 2040(sp)
24-
; CHECK-NEXT: sw a5, 2044(sp)
25-
; CHECK-NEXT: sw a6, 2032(sp)
26-
; CHECK-NEXT: sw a7, 2036(sp)
21+
; CHECK-NEXT: sw a2, -2048(a0) # 4-byte Folded Spill
22+
; CHECK-NEXT: sw a3, -2044(a0) # 4-byte Folded Spill
23+
; CHECK-NEXT: sw a4, 2040(sp) # 4-byte Folded Spill
24+
; CHECK-NEXT: sw a5, 2044(sp) # 4-byte Folded Spill
25+
; CHECK-NEXT: sw a6, 2032(sp) # 4-byte Folded Spill
26+
; CHECK-NEXT: sw a7, 2036(sp) # 4-byte Folded Spill
2727
; CHECK-NEXT: lui a0, 1
2828
; CHECK-NEXT: add a0, sp, a0
29-
; CHECK-NEXT: lw a1, -2036(a0)
30-
; CHECK-NEXT: lw a0, -2040(a0)
29+
; CHECK-NEXT: lw a1, -2036(a0) # 4-byte Folded Reload
30+
; CHECK-NEXT: lw a0, -2040(a0) # 4-byte Folded Reload
3131
; CHECK-NEXT: lui a0, 1
3232
; CHECK-NEXT: add a0, sp, a0
33-
; CHECK-NEXT: lw a2, -2048(a0)
34-
; CHECK-NEXT: lw a3, -2044(a0)
35-
; CHECK-NEXT: lw a4, 2040(sp)
36-
; CHECK-NEXT: lw a5, 2044(sp)
37-
; CHECK-NEXT: lw a6, 2032(sp)
38-
; CHECK-NEXT: lw a7, 2036(sp)
33+
; CHECK-NEXT: lw a2, -2048(a0) # 4-byte Folded Reload
34+
; CHECK-NEXT: lw a3, -2044(a0) # 4-byte Folded Reload
35+
; CHECK-NEXT: lw a4, 2040(sp) # 4-byte Folded Reload
36+
; CHECK-NEXT: lw a5, 2044(sp) # 4-byte Folded Reload
37+
; CHECK-NEXT: lw a6, 2032(sp) # 4-byte Folded Reload
38+
; CHECK-NEXT: lw a7, 2036(sp) # 4-byte Folded Reload
3939
; CHECK-NEXT: addi sp, sp, 2032
4040
; CHECK-NEXT: addi sp, sp, 32
4141
; CHECK-NEXT: ret

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