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koachankoachan
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[𝘀𝗽𝗿] initial version
Created using spr 1.3.5
2 parents 5d0e26e + 8e75442 commit 71fe8f9

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-85
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19 files changed

+1184
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‎llvm/include/llvm/BinaryFormat/ELFRelocs/Sparc.def‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -87,3 +87,4 @@ ELF_RELOC(R_SPARC_GOTDATA_LOX10, 81)
8787
ELF_RELOC(R_SPARC_GOTDATA_OP_HIX22, 82)
8888
ELF_RELOC(R_SPARC_GOTDATA_OP_LOX10, 83)
8989
ELF_RELOC(R_SPARC_GOTDATA_OP, 84)
90+
ELF_RELOC(R_SPARC_WDISP10, 88)

‎llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -261,6 +261,8 @@ DecodeCoprocPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
261261

262262
static DecodeStatus DecodeCall(MCInst &Inst, unsigned insn, uint64_t Address,
263263
const MCDisassembler *Decoder);
264+
static DecodeStatus DecodeSIMM5(MCInst &Inst, unsigned insn, uint64_t Address,
265+
const MCDisassembler *Decoder);
264266
static DecodeStatus DecodeSIMM13(MCInst &Inst, unsigned insn, uint64_t Address,
265267
const MCDisassembler *Decoder);
266268

@@ -340,6 +342,13 @@ static DecodeStatus DecodeCall(MCInst &MI, unsigned insn, uint64_t Address,
340342
return MCDisassembler::Success;
341343
}
342344

345+
static DecodeStatus DecodeSIMM5(MCInst &MI, unsigned insn, uint64_t Address,
346+
const MCDisassembler *Decoder) {
347+
assert(isUInt<5>(insn));
348+
MI.addOperand(MCOperand::createImm(SignExtend64<5>(insn)));
349+
return MCDisassembler::Success;
350+
}
351+
343352
static DecodeStatus DecodeSIMM13(MCInst &MI, unsigned insn, uint64_t Address,
344353
const MCDisassembler *Decoder) {
345354
assert(isUInt<13>(insn));

‎llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp‎

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -50,6 +50,15 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
5050
return (d16hi << 20) | d16lo;
5151
}
5252

53+
case Sparc::fixup_sparc_br10: {
54+
// 7.17 Compare and Branch
55+
// Inst{20-19} = d10hi;
56+
// Inst{12-5} = d10lo;
57+
unsigned d10hi = (Value >> 10) & 0x3;
58+
unsigned d10lo = (Value >> 2) & 0xff;
59+
return (d10hi << 19) | (d10lo << 5);
60+
}
61+
5362
case Sparc::fixup_sparc_hix22:
5463
return (~Value >> 10) & 0x3fffff;
5564

@@ -162,11 +171,13 @@ namespace {
162171

163172
MCFixupKindInfo getFixupKindInfo(MCFixupKind Kind) const override {
164173
const static MCFixupKindInfo InfosBE[Sparc::NumTargetFixupKinds] = {
174+
// clang-format off
165175
// name offset bits flags
166176
{ "fixup_sparc_call30", 2, 30, MCFixupKindInfo::FKF_IsPCRel },
167177
{ "fixup_sparc_br22", 10, 22, MCFixupKindInfo::FKF_IsPCRel },
168178
{ "fixup_sparc_br19", 13, 19, MCFixupKindInfo::FKF_IsPCRel },
169179
{ "fixup_sparc_br16", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
180+
{ "fixup_sparc_br10", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
170181
{ "fixup_sparc_13", 19, 13, 0 },
171182
{ "fixup_sparc_hi22", 10, 22, 0 },
172183
{ "fixup_sparc_lo10", 22, 10, 0 },
@@ -205,14 +216,17 @@ namespace {
205216
{ "fixup_sparc_gotdata_hix22", 0, 0, 0 },
206217
{ "fixup_sparc_gotdata_lox10", 0, 0, 0 },
207218
{ "fixup_sparc_gotdata_op", 0, 0, 0 },
219+
// clang-format on
208220
};
209221

210222
const static MCFixupKindInfo InfosLE[Sparc::NumTargetFixupKinds] = {
223+
// clang-format off
211224
// name offset bits flags
212225
{ "fixup_sparc_call30", 0, 30, MCFixupKindInfo::FKF_IsPCRel },
213226
{ "fixup_sparc_br22", 0, 22, MCFixupKindInfo::FKF_IsPCRel },
214227
{ "fixup_sparc_br19", 0, 19, MCFixupKindInfo::FKF_IsPCRel },
215228
{ "fixup_sparc_br16", 32, 0, MCFixupKindInfo::FKF_IsPCRel },
229+
{ "fixup_sparc_br10", 32, 0, MCFixupKindInfo::FKF_IsPCRel },
216230
{ "fixup_sparc_13", 0, 13, 0 },
217231
{ "fixup_sparc_hi22", 0, 22, 0 },
218232
{ "fixup_sparc_lo10", 0, 10, 0 },
@@ -251,6 +265,7 @@ namespace {
251265
{ "fixup_sparc_gotdata_hix22", 0, 0, 0 },
252266
{ "fixup_sparc_gotdata_lox10", 0, 0, 0 },
253267
{ "fixup_sparc_gotdata_op", 0, 0, 0 },
268+
// clang-format on
254269
};
255270

256271
// Fixup kinds from .reloc directive are like R_SPARC_NONE. They do

‎llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -84,6 +84,8 @@ unsigned SparcELFObjectWriter::getRelocType(MCContext &Ctx,
8484
case Sparc::fixup_sparc_br19: return ELF::R_SPARC_WDISP19;
8585
case Sparc::fixup_sparc_br16:
8686
return ELF::R_SPARC_WDISP16;
87+
case Sparc::fixup_sparc_br10:
88+
return ELF::R_SPARC_WDISP10;
8789
case Sparc::fixup_sparc_pc22: return ELF::R_SPARC_PC22;
8890
case Sparc::fixup_sparc_pc10: return ELF::R_SPARC_PC10;
8991
case Sparc::fixup_sparc_wplt30: return ELF::R_SPARC_WPLT30;

‎llvm/lib/Target/Sparc/MCTargetDesc/SparcFixupKinds.h‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@
1111

1212
#include "llvm/MC/MCFixup.h"
1313

14+
// clang-format off
1415
namespace llvm {
1516
namespace Sparc {
1617
enum Fixups {
@@ -28,6 +29,9 @@ namespace llvm {
2829
/// fixup_sparc_bpr - 16-bit fixup for bpr
2930
fixup_sparc_br16,
3031

32+
/// fixup_sparc_br10 - 10-bit fixup for cbcond
33+
fixup_sparc_br10,
34+
3135
/// fixup_sparc_13 - 13-bit fixup
3236
fixup_sparc_13,
3337

@@ -112,5 +116,5 @@ namespace llvm {
112116
};
113117
}
114118
}
115-
119+
// clang-format on
116120
#endif

‎llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -192,8 +192,8 @@ void SparcInstPrinter::printCCOperand(const MCInst *MI, int opNum,
192192
// Make sure CC is a fp conditional flag.
193193
CC = (CC < SPCC::FCC_BEGIN) ? (CC + SPCC::FCC_BEGIN) : CC;
194194
break;
195-
case SP::CBCOND:
196-
case SP::CBCONDA:
195+
case SP::CPBCOND:
196+
case SP::CPBCONDA:
197197
// Make sure CC is a cp conditional flag.
198198
CC = (CC < SPCC::CPCC_BEGIN) ? (CC + SPCC::CPCC_BEGIN) : CC;
199199
break;

‎llvm/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp‎

Lines changed: 39 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -71,6 +71,9 @@ class SparcMCCodeEmitter : public MCCodeEmitter {
7171
unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
7272
SmallVectorImpl<MCFixup> &Fixups,
7373
const MCSubtargetInfo &STI) const;
74+
unsigned getSImm5OpValue(const MCInst &MI, unsigned OpNo,
75+
SmallVectorImpl<MCFixup> &Fixups,
76+
const MCSubtargetInfo &STI) const;
7477
unsigned getSImm13OpValue(const MCInst &MI, unsigned OpNo,
7578
SmallVectorImpl<MCFixup> &Fixups,
7679
const MCSubtargetInfo &STI) const;
@@ -80,6 +83,9 @@ class SparcMCCodeEmitter : public MCCodeEmitter {
8083
unsigned getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo,
8184
SmallVectorImpl<MCFixup> &Fixups,
8285
const MCSubtargetInfo &STI) const;
86+
unsigned getCompareAndBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
87+
SmallVectorImpl<MCFixup> &Fixups,
88+
const MCSubtargetInfo &STI) const;
8389
};
8490

8591
} // end anonymous namespace
@@ -141,6 +147,26 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO,
141147
return 0;
142148
}
143149

150+
unsigned SparcMCCodeEmitter::getSImm5OpValue(const MCInst &MI, unsigned OpNo,
151+
SmallVectorImpl<MCFixup> &Fixups,
152+
const MCSubtargetInfo &STI) const {
153+
const MCOperand &MO = MI.getOperand(OpNo);
154+
155+
if (MO.isImm())
156+
return MO.getImm();
157+
158+
assert(MO.isExpr() &&
159+
"getSImm5OpValue expects only expressions or an immediate");
160+
161+
const MCExpr *Expr = MO.getExpr();
162+
163+
// Constant value, no fixup is needed
164+
if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
165+
return CE->getValue();
166+
167+
llvm_unreachable("simm5 operands can only be used with constants!");
168+
}
169+
144170
unsigned
145171
SparcMCCodeEmitter::getSImm13OpValue(const MCInst &MI, unsigned OpNo,
146172
SmallVectorImpl<MCFixup> &Fixups,
@@ -239,6 +265,19 @@ getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo,
239265
return 0;
240266
}
241267

268+
unsigned SparcMCCodeEmitter::getCompareAndBranchTargetOpValue(
269+
const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups,
270+
const MCSubtargetInfo &STI) const {
271+
const MCOperand &MO = MI.getOperand(OpNo);
272+
if (MO.isReg() || MO.isImm())
273+
return getMachineOpValue(MI, MO, Fixups, STI);
274+
275+
Fixups.push_back(
276+
MCFixup::create(0, MO.getExpr(), (MCFixupKind)Sparc::fixup_sparc_br10));
277+
278+
return 0;
279+
}
280+
242281
#include "SparcGenMCCodeEmitter.inc"
243282

244283
MCCodeEmitter *llvm::createSparcMCCodeEmitter(const MCInstrInfo &MCII,

‎llvm/lib/Target/Sparc/Sparc.td‎

Lines changed: 15 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -49,6 +49,15 @@ def FeatureVIS2
4949
def FeatureVIS3
5050
: SubtargetFeature<"vis3", "IsVIS3", "true",
5151
"Enable Visual Instruction Set extensions III">;
52+
def FeatureUA2005
53+
: SubtargetFeature<"ua2005", "IsUA2005", "true",
54+
"Enable UltraSPARC Architecture 2005 extensions">;
55+
def FeatureUA2007
56+
: SubtargetFeature<"ua2007", "IsUA2007", "true",
57+
"Enable UltraSPARC Architecture 2007 extensions">;
58+
def FeatureOSA2011
59+
: SubtargetFeature<"osa2011", "IsOSA2011", "true",
60+
"Enable Oracle SPARC Architecture 2011 extensions">;
5261
def FeatureLeon
5362
: SubtargetFeature<"leon", "IsLeon", "true",
5463
"Enable LEON extensions">;
@@ -152,13 +161,15 @@ def : Proc<"ultrasparc3", [FeatureV9, FeatureV8Deprecated, FeatureVIS,
152161
FeatureVIS2],
153162
[TuneSlowRDPC]>;
154163
def : Proc<"niagara", [FeatureV9, FeatureV8Deprecated, FeatureVIS,
155-
FeatureVIS2]>;
164+
FeatureVIS2, FeatureUA2005]>;
156165
def : Proc<"niagara2", [FeatureV9, FeatureV8Deprecated, UsePopc,
157-
FeatureVIS, FeatureVIS2]>;
166+
FeatureVIS, FeatureVIS2, FeatureUA2005]>;
158167
def : Proc<"niagara3", [FeatureV9, FeatureV8Deprecated, UsePopc,
159-
FeatureVIS, FeatureVIS2]>;
168+
FeatureVIS, FeatureVIS2, FeatureVIS3,
169+
FeatureUA2005, FeatureUA2007]>;
160170
def : Proc<"niagara4", [FeatureV9, FeatureV8Deprecated, UsePopc,
161-
FeatureVIS, FeatureVIS2, FeatureVIS3]>;
171+
FeatureVIS, FeatureVIS2, FeatureVIS3,
172+
FeatureUA2005, FeatureUA2007, FeatureOSA2011]>;
162173

163174
// LEON 2 FT generic
164175
def : Processor<"leon2", LEON2Itineraries,

‎llvm/lib/Target/Sparc/SparcInstr64Bit.td‎

Lines changed: 3 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -180,37 +180,13 @@ def : Pat<(i64 (ctpop i64:$src)), (POPCrr $src)>;
180180
//===----------------------------------------------------------------------===//
181181

182182
let Predicates = [Is64Bit] in {
183-
184-
def MULXrr : F3_1<2, 0b001001,
185-
(outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
186-
"mulx $rs1, $rs2, $rd",
187-
[(set i64:$rd, (mul i64:$rs1, i64:$rs2))]>;
188-
def MULXri : F3_2<2, 0b001001,
189-
(outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
190-
"mulx $rs1, $simm13, $rd",
191-
[(set i64:$rd, (mul i64:$rs1, (i64 simm13:$simm13)))]>;
183+
defm MULX : F3_12<"mulx", 0b001001, mul, I64Regs, i64, i64imm>;
192184

193185
// Division can trap.
194186
let hasSideEffects = 1 in {
195-
def SDIVXrr : F3_1<2, 0b101101,
196-
(outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
197-
"sdivx $rs1, $rs2, $rd",
198-
[(set i64:$rd, (sdiv i64:$rs1, i64:$rs2))]>;
199-
def SDIVXri : F3_2<2, 0b101101,
200-
(outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
201-
"sdivx $rs1, $simm13, $rd",
202-
[(set i64:$rd, (sdiv i64:$rs1, (i64 simm13:$simm13)))]>;
203-
204-
def UDIVXrr : F3_1<2, 0b001101,
205-
(outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
206-
"udivx $rs1, $rs2, $rd",
207-
[(set i64:$rd, (udiv i64:$rs1, i64:$rs2))]>;
208-
def UDIVXri : F3_2<2, 0b001101,
209-
(outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
210-
"udivx $rs1, $simm13, $rd",
211-
[(set i64:$rd, (udiv i64:$rs1, (i64 simm13:$simm13)))]>;
187+
defm SDIVX : F3_12<"sdivx", 0b101101, sdiv, I64Regs, i64, i64imm>;
188+
defm UDIVX : F3_12<"udivx", 0b001101, udiv, I64Regs, i64, i64imm>;
212189
} // hasSideEffects = 1
213-
214190
} // Predicates = [Is64Bit]
215191

216192

‎llvm/lib/Target/Sparc/SparcInstrAliases.td‎

Lines changed: 67 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -286,11 +286,11 @@ multiclass cp_cond_alias<string cond, int condVal> {
286286

287287
// cb<cond> $imm
288288
def : InstAlias<!strconcat(!strconcat("cb", cond), " $imm"),
289-
(CBCOND brtarget:$imm, condVal), 0>;
289+
(CPBCOND brtarget:$imm, condVal), 0>;
290290

291291
// cb<cond>,a $imm
292292
def : InstAlias<!strconcat(!strconcat("cb", cond), ",a $imm"),
293-
(CBCONDA brtarget:$imm, condVal), 0>;
293+
(CPBCONDA brtarget:$imm, condVal), 0>;
294294
}
295295

296296
// Instruction aliases for register conditional branches and moves.
@@ -331,6 +331,25 @@ multiclass reg_cond_alias<string rcond, int condVal> {
331331
Requires<[Is64Bit]>;
332332
}
333333

334+
// Instruction aliases for compare-and-branch.
335+
multiclass cwb_cond_alias<string cond, int condVal> {
336+
def : InstAlias<!strconcat(!strconcat("cwb", cond), " $rs1, $rs2, $imm"),
337+
(CWBCONDrr cbtarget:$imm, condVal, IntRegs:$rs1, IntRegs:$rs2)>,
338+
Requires<[HasOSA2011]>;
339+
def : InstAlias<!strconcat(!strconcat("cwb", cond), " $rs1, $simm5, $imm"),
340+
(CWBCONDri cbtarget:$imm, condVal, IntRegs:$rs1, simm5Op:$simm5)>,
341+
Requires<[HasOSA2011]>;
342+
}
343+
344+
multiclass cxb_cond_alias<string cond, int condVal> {
345+
def : InstAlias<!strconcat(!strconcat("cxb", cond), " $rs1, $rs2, $imm"),
346+
(CXBCONDrr cbtarget:$imm, condVal, IntRegs:$rs1, IntRegs:$rs2)>,
347+
Requires<[HasOSA2011]>;
348+
def : InstAlias<!strconcat(!strconcat("cxb", cond), " $rs1, $simm5, $imm"),
349+
(CXBCONDri cbtarget:$imm, condVal, IntRegs:$rs1, simm5Op:$simm5)>,
350+
Requires<[HasOSA2011]>;
351+
}
352+
334353
defm : int_cond_alias<"a", 0b1000>;
335354
defm : int_cond_alias<"n", 0b0000>;
336355
defm : int_cond_alias<"ne", 0b1001>;
@@ -408,6 +427,46 @@ defm : reg_cond_alias<"ne", 0b101>;
408427
defm : reg_cond_alias<"gz", 0b110>;
409428
defm : reg_cond_alias<"gez", 0b111>;
410429

430+
defm : cwb_cond_alias<"ne", 0b1001>;
431+
defm : cwb_cond_alias<"e", 0b0001>;
432+
defm : cwb_cond_alias<"g", 0b1010>;
433+
defm : cwb_cond_alias<"le", 0b0010>;
434+
defm : cwb_cond_alias<"ge", 0b1011>;
435+
defm : cwb_cond_alias<"l", 0b0011>;
436+
defm : cwb_cond_alias<"gu", 0b1100>;
437+
defm : cwb_cond_alias<"leu", 0b0100>;
438+
defm : cwb_cond_alias<"cc", 0b1101>;
439+
defm : cwb_cond_alias<"cs", 0b0101>;
440+
defm : cwb_cond_alias<"pos", 0b1110>;
441+
defm : cwb_cond_alias<"neg", 0b0110>;
442+
defm : cwb_cond_alias<"vc", 0b1111>;
443+
defm : cwb_cond_alias<"vs", 0b0111>;
444+
let EmitPriority = 0 in
445+
{
446+
defm : cwb_cond_alias<"geu", 0b1101>; // same as cc
447+
defm : cwb_cond_alias<"lu", 0b0101>; // same as cs
448+
}
449+
450+
defm : cxb_cond_alias<"ne", 0b1001>;
451+
defm : cxb_cond_alias<"e", 0b0001>;
452+
defm : cxb_cond_alias<"g", 0b1010>;
453+
defm : cxb_cond_alias<"le", 0b0010>;
454+
defm : cxb_cond_alias<"ge", 0b1011>;
455+
defm : cxb_cond_alias<"l", 0b0011>;
456+
defm : cxb_cond_alias<"gu", 0b1100>;
457+
defm : cxb_cond_alias<"leu", 0b0100>;
458+
defm : cxb_cond_alias<"cc", 0b1101>;
459+
defm : cxb_cond_alias<"cs", 0b0101>;
460+
defm : cxb_cond_alias<"pos", 0b1110>;
461+
defm : cxb_cond_alias<"neg", 0b0110>;
462+
defm : cxb_cond_alias<"vc", 0b1111>;
463+
defm : cxb_cond_alias<"vs", 0b0111>;
464+
let EmitPriority = 0 in
465+
{
466+
defm : cxb_cond_alias<"geu", 0b1101>; // same as cc
467+
defm : cxb_cond_alias<"lu", 0b0101>; // same as cs
468+
}
469+
411470
// Section A.3 Synthetic Instructions
412471

413472
// Most are marked as Emit=0, so that they are not used for disassembly. This is
@@ -665,3 +724,9 @@ def : InstAlias<"signx $rs1, $rd", (SRArr IntRegs:$rd, IntRegs:$rs1, G0), 0>, Re
665724

666725
// sir -> sir 0
667726
def : InstAlias<"sir", (SIR 0), 0>;
727+
728+
// pause reg_or_imm -> wrasr %g0, reg_or_imm, %asr27
729+
let Predicates = [HasOSA2011] in {
730+
def : InstAlias<"pause $rs2", (WRASRrr ASR27, G0, IntRegs:$rs2), 1>;
731+
def : InstAlias<"pause $simm13", (WRASRri ASR27, G0, simm13Op:$simm13), 1>;
732+
} // Predicates = [HasOSA2011]

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