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Fixes for issues reported when landing #134408
The register coalescer ran into some asserts: * The newly added code tried to get the LiveInterval for a physical register (unguarded path) * The assert 'assert(SubregToRegSrcInsts.empty() && "can this happen?");' could happen when using SUBREG_TO_REG to say that the top bits of the second register in a {128, 128} register tuple are zero, e.g. %8.qsub1:qq = MOVIv2d_ns 0 %4:zpr = SUBREG_TO_REG 0, %8.qsub1:qq, %subreg.zsub
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+276
-89
lines changed

9 files changed

+276
-89
lines changed

‎llvm/lib/CodeGen/RegisterCoalescer.cpp‎

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2301,7 +2301,8 @@ bool RegisterCoalescer::joinCopy(
23012301
}
23022302

23032303
SmallVector<MachineInstr *> SubregToRegSrcInsts;
2304-
if (CopyMI->isSubregToReg()) {
2304+
Register SrcReg = CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg();
2305+
if (CopyMI->isSubregToReg() && !SrcReg.isPhysical()) {
23052306
// For the case where the copy instruction is a SUBREG_TO_REG, e.g.
23062307
//
23072308
// %0:gpr32 = movimm32 ..
@@ -2319,8 +2320,7 @@ bool RegisterCoalescer::joinCopy(
23192320
// // require an implicit-def,
23202321
// // because it has nothing to
23212322
// // do with the SUBREG_TO_REG.
2322-
LiveInterval &SrcInt =
2323-
LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
2323+
LiveInterval &SrcInt = LIS->getInterval(SrcReg);
23242324
SlotIndex SubregToRegSlotIdx = LIS->getInstructionIndex(*CopyMI);
23252325
SmallPtrSet<MachineBasicBlock *, 8> VisitedBlocks;
23262326
if (!FindDefInBlock(VisitedBlocks, SubregToRegSrcInsts, LIS, SrcInt,
@@ -2397,10 +2397,8 @@ bool RegisterCoalescer::joinCopy(
23972397

23982398
// Rewrite all SrcReg operands to DstReg.
23992399
// Also update DstReg operands to include DstIdx if it is set.
2400-
if (CP.getDstIdx()) {
2401-
assert(SubregToRegSrcInsts.empty() && "can this happen?");
2400+
if (CP.getDstIdx())
24022401
updateRegDefsUses(CP.getDstReg(), CP.getDstReg(), CP.getDstIdx());
2403-
}
24042402
updateRegDefsUses(CP.getSrcReg(), CP.getDstReg(), CP.getSrcIdx(),
24052403
SubregToRegSrcInsts);
24062404

‎llvm/test/CodeGen/AArch64/pr151592.mir‎

Lines changed: 168 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,168 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
2+
# RUN: llc -mtriple=aarch64 -run-pass=register-coalescer -o - %s | FileCheck %s
3+
---
4+
name: reproducer
5+
tracksRegLiveness: true
6+
body: |
7+
; CHECK-LABEL: name: reproducer
8+
; CHECK: bb.0:
9+
; CHECK-NEXT: successors: %bb.1(0x80000000)
10+
; CHECK-NEXT: liveins: $w0, $x1
11+
; CHECK-NEXT: {{ $}}
12+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x1
13+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
14+
; CHECK-NEXT: undef [[MOVIv2d_ns:%[0-9]+]].qsub1:zpr2 = MOVIv2d_ns 0, implicit-def [[MOVIv2d_ns]]
15+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64sp = COPY $xzr
16+
; CHECK-NEXT: {{ $}}
17+
; CHECK-NEXT: bb.1:
18+
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
19+
; CHECK-NEXT: {{ $}}
20+
; CHECK-NEXT: TBNZW [[COPY1]], 0, %bb.3
21+
; CHECK-NEXT: B %bb.2
22+
; CHECK-NEXT: {{ $}}
23+
; CHECK-NEXT: bb.2:
24+
; CHECK-NEXT: successors: %bb.3(0x80000000)
25+
; CHECK-NEXT: {{ $}}
26+
; CHECK-NEXT: [[MOVIv2d_ns:%[0-9]+]].dsub:zpr2 = LDRDui [[COPY2]], 0, implicit-def [[MOVIv2d_ns]].zsub
27+
; CHECK-NEXT: ST2Twov2d [[MOVIv2d_ns]].zsub_qsub1, [[COPY]]
28+
; CHECK-NEXT: {{ $}}
29+
; CHECK-NEXT: bb.3:
30+
; CHECK-NEXT: successors: %bb.1(0x80000000)
31+
; CHECK-NEXT: {{ $}}
32+
; CHECK-NEXT: STR_ZXI [[MOVIv2d_ns]].zsub1, [[COPY]], 1
33+
; CHECK-NEXT: STR_ZXI [[MOVIv2d_ns]].zsub1, [[COPY]], 0
34+
; CHECK-NEXT: B %bb.1
35+
bb.0:
36+
liveins: $w0, $x1
37+
%0:gpr64common = COPY $x1
38+
%1:gpr32 = COPY $w0
39+
%2:gpr32 = COPY %1:gpr32
40+
undef %8.qsub1:qq = MOVIv2d_ns 0
41+
%4:zpr = SUBREG_TO_REG 0, %8.qsub1:qq, %subreg.zsub
42+
%5:gpr64sp = COPY $xzr
43+
44+
bb.1:
45+
TBNZW %2:gpr32, 0, %bb.3
46+
B %bb.2
47+
48+
bb.2:
49+
%8.dsub:qq = LDRDui %5:gpr64sp, 0, implicit-def %8.qsub0:qq
50+
ST2Twov2d %8:qq, %0:gpr64common
51+
52+
bb.3:
53+
STR_ZXI %4:zpr, %0:gpr64common, 1
54+
STR_ZXI %4:zpr, %0:gpr64common, 0
55+
B %bb.1
56+
...
57+
---
58+
name: reproducer2
59+
tracksRegLiveness: true
60+
body: |
61+
; CHECK-LABEL: name: reproducer2
62+
; CHECK: bb.0:
63+
; CHECK-NEXT: successors: %bb.1(0x80000000)
64+
; CHECK-NEXT: liveins: $w0, $x1
65+
; CHECK-NEXT: {{ $}}
66+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x1
67+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
68+
; CHECK-NEXT: undef [[MOVIv2d_ns:%[0-9]+]].zsub:zpr2 = MOVIv2d_ns 0
69+
; CHECK-NEXT: [[MOVIv2d_ns:%[0-9]+]].qsub1:zpr2 = MOVIv2d_ns 0
70+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64sp = COPY $xzr
71+
; CHECK-NEXT: {{ $}}
72+
; CHECK-NEXT: bb.1:
73+
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
74+
; CHECK-NEXT: {{ $}}
75+
; CHECK-NEXT: TBNZW [[COPY1]], 0, %bb.3
76+
; CHECK-NEXT: B %bb.2
77+
; CHECK-NEXT: {{ $}}
78+
; CHECK-NEXT: bb.2:
79+
; CHECK-NEXT: successors: %bb.3(0x80000000)
80+
; CHECK-NEXT: {{ $}}
81+
; CHECK-NEXT: [[MOVIv2d_ns:%[0-9]+]].dsub:zpr2 = LDRDui [[COPY2]], 0, implicit-def [[MOVIv2d_ns]].zsub
82+
; CHECK-NEXT: ST2Twov2d [[MOVIv2d_ns]].zsub_qsub1, [[COPY]]
83+
; CHECK-NEXT: {{ $}}
84+
; CHECK-NEXT: bb.3:
85+
; CHECK-NEXT: successors: %bb.1(0x80000000)
86+
; CHECK-NEXT: {{ $}}
87+
; CHECK-NEXT: STR_ZXI [[MOVIv2d_ns]].zsub1, [[COPY]], 1
88+
; CHECK-NEXT: STR_ZXI [[MOVIv2d_ns]].zsub1, [[COPY]], 0
89+
; CHECK-NEXT: B %bb.1
90+
bb.0:
91+
liveins: $w0, $x1
92+
%0:gpr64common = COPY $x1
93+
%1:gpr32 = COPY $w0
94+
%2:gpr32 = COPY %1:gpr32
95+
undef %8.qsub0:qq = MOVIv2d_ns 0
96+
%8.qsub1:qq = MOVIv2d_ns 0
97+
%4:zpr = SUBREG_TO_REG 0, %8.qsub1:qq, %subreg.zsub
98+
%5:gpr64sp = COPY $xzr
99+
100+
bb.1:
101+
TBNZW %2:gpr32, 0, %bb.3
102+
B %bb.2
103+
104+
bb.2:
105+
%8.dsub:qq = LDRDui %5:gpr64sp, 0, implicit-def %8.qsub0:qq
106+
ST2Twov2d %8:qq, %0:gpr64common
107+
108+
bb.3:
109+
STR_ZXI %4:zpr, %0:gpr64common, 1
110+
STR_ZXI %4:zpr, %0:gpr64common, 0
111+
B %bb.1
112+
...
113+
---
114+
name: reproducer3
115+
tracksRegLiveness: true
116+
body: |
117+
; CHECK-LABEL: name: reproducer3
118+
; CHECK: bb.0:
119+
; CHECK-NEXT: successors: %bb.1(0x80000000)
120+
; CHECK-NEXT: liveins: $w0, $x1
121+
; CHECK-NEXT: {{ $}}
122+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x1
123+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
124+
; CHECK-NEXT: undef [[MOVIv2d_ns:%[0-9]+]].qsub1:zpr2 = MOVIv2d_ns 0
125+
; CHECK-NEXT: [[MOVIv2d_ns:%[0-9]+]].zsub:zpr2 = MOVIv2d_ns 0
126+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64sp = COPY $xzr
127+
; CHECK-NEXT: {{ $}}
128+
; CHECK-NEXT: bb.1:
129+
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
130+
; CHECK-NEXT: {{ $}}
131+
; CHECK-NEXT: TBNZW [[COPY1]], 0, %bb.3
132+
; CHECK-NEXT: B %bb.2
133+
; CHECK-NEXT: {{ $}}
134+
; CHECK-NEXT: bb.2:
135+
; CHECK-NEXT: successors: %bb.3(0x80000000)
136+
; CHECK-NEXT: {{ $}}
137+
; CHECK-NEXT: [[MOVIv2d_ns:%[0-9]+]].dsub1:zpr2 = LDRDui [[COPY2]], 0, implicit-def [[MOVIv2d_ns]].qsub1
138+
; CHECK-NEXT: ST2Twov2d [[MOVIv2d_ns]].zsub_qsub1, [[COPY]]
139+
; CHECK-NEXT: {{ $}}
140+
; CHECK-NEXT: bb.3:
141+
; CHECK-NEXT: successors: %bb.1(0x80000000)
142+
; CHECK-NEXT: {{ $}}
143+
; CHECK-NEXT: STR_ZXI [[MOVIv2d_ns]].zsub0, [[COPY]], 1
144+
; CHECK-NEXT: STR_ZXI [[MOVIv2d_ns]].zsub0, [[COPY]], 0
145+
; CHECK-NEXT: B %bb.1
146+
bb.0:
147+
liveins: $w0, $x1
148+
%0:gpr64common = COPY $x1
149+
%1:gpr32 = COPY $w0
150+
%2:gpr32 = COPY %1:gpr32
151+
undef %8.qsub1:qq = MOVIv2d_ns 0
152+
%8.qsub0:qq = MOVIv2d_ns 0
153+
%4:zpr = SUBREG_TO_REG 0, %8.qsub0:qq, %subreg.zsub
154+
%5:gpr64sp = COPY $xzr
155+
156+
bb.1:
157+
TBNZW %2:gpr32, 0, %bb.3
158+
B %bb.2
159+
160+
bb.2:
161+
%8.dsub1:qq = LDRDui %5:gpr64sp, 0, implicit-def %8.qsub1:qq
162+
ST2Twov2d %8:qq, %0:gpr64common
163+
164+
bb.3:
165+
STR_ZXI %4:zpr, %0:gpr64common, 1
166+
STR_ZXI %4:zpr, %0:gpr64common, 0
167+
B %bb.1
168+
...

‎llvm/test/CodeGen/AArch64/pr151888.mir‎

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,17 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
2+
# RUN: llc -mtriple=aarch64 -run-pass=register-coalescer -o - %s | FileCheck %s
3+
---
4+
name: reproducer
5+
tracksRegLiveness: true
6+
body: |
7+
bb.0.entry:
8+
; CHECK-LABEL: name: reproducer
9+
; CHECK: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri $xzr, 0, 31
10+
; CHECK-NEXT: $x0 = COPY [[UBFMXri]]
11+
; CHECK-NEXT: RET_ReallyLR implicit $x0
12+
%1:gpr32 = COPY killed $wzr
13+
%2:gpr64 = SUBREG_TO_REG 0, %1:gpr32, %subreg.sub_32
14+
%3:gpr64 = UBFMXri %2:gpr64, 0, 31
15+
$x0 = COPY %3:gpr64
16+
RET_ReallyLR implicit $x0
17+
...

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