revert rename for spv

Author: KungFuDonkey

clang/test/CodeGenHLSL/builtins/WaveActiveProduct.hlsl

@@ -9,37 +9,37 @@
 
 // CHECK-LABEL: test_int
 int test_int(int expr) {
-  // CHECK-SPIRV:  %[[RET:.*]] = call spir_func [[TY:.*]] @llvm.spv.wave.product.i32([[TY]] %[[#]])
+  // CHECK-SPIRV:  %[[RET:.*]] = call spir_func [[TY:.*]] @llvm.spv.wave.reduce.product.i32([[TY]] %[[#]])
   // CHECK-DXIL:  %[[RET:.*]] = call [[TY:.*]] @llvm.dx.wave.product.i32([[TY]] %[[#]])
   // CHECK:  ret [[TY]] %[[RET]]
   return WaveActiveProduct(expr);
 }
 
 // CHECK-DXIL: declare [[TY]] @llvm.dx.wave.product.i32([[TY]]) #[[#attr:]]
-// CHECK-SPIRV: declare [[TY]] @llvm.spv.wave.product.i32([[TY]]) #[[#attr:]]
+// CHECK-SPIRV: declare [[TY]] @llvm.spv.wave.reduce.product.i32([[TY]]) #[[#attr:]]
 
 // CHECK-LABEL: test_uint64_t
 uint64_t test_uint64_t(uint64_t expr) {
-  // CHECK-SPIRV:  %[[RET:.*]] = call spir_func [[TY:.*]] @llvm.spv.wave.product.i64([[TY]] %[[#]])
+  // CHECK-SPIRV:  %[[RET:.*]] = call spir_func [[TY:.*]] @llvm.spv.wave.reduce.product.i64([[TY]] %[[#]])
   // CHECK-DXIL:  %[[RET:.*]] = call [[TY:.*]] @llvm.dx.wave.uproduct.i64([[TY]] %[[#]])
   // CHECK:  ret [[TY]] %[[RET]]
   return WaveActiveProduct(expr);
 }
 
 // CHECK-DXIL: declare [[TY]] @llvm.dx.wave.uproduct.i64([[TY]]) #[[#attr:]]
-// CHECK-SPIRV: declare [[TY]] @llvm.spv.wave.product.i64([[TY]]) #[[#attr:]]
+// CHECK-SPIRV: declare [[TY]] @llvm.spv.wave.reduce.product.i64([[TY]]) #[[#attr:]]
 
 // Test basic lowering to runtime function call with array and float value.
 
 // CHECK-LABEL: test_floatv4
 float4 test_floatv4(float4 expr) {
-  // CHECK-SPIRV:  %[[RET1:.*]] = call reassoc nnan ninf nsz arcp afn spir_func [[TY1:.*]] @llvm.spv.wave.product.v4f32([[TY1]] %[[#]]
+  // CHECK-SPIRV:  %[[RET1:.*]] = call reassoc nnan ninf nsz arcp afn spir_func [[TY1:.*]] @llvm.spv.wave.reduce.product.v4f32([[TY1]] %[[#]]
   // CHECK-DXIL:  %[[RET1:.*]] = call reassoc nnan ninf nsz arcp afn [[TY1:.*]] @llvm.dx.wave.product.v4f32([[TY1]] %[[#]])
   // CHECK:  ret [[TY1]] %[[RET1]]
   return WaveActiveProduct(expr);
 }
 
 // CHECK-DXIL: declare [[TY1]] @llvm.dx.wave.product.v4f32([[TY1]]) #[[#attr]]
-// CHECK-SPIRV: declare [[TY1]] @llvm.spv.wave.product.v4f32([[TY1]]) #[[#attr]]
+// CHECK-SPIRV: declare [[TY1]] @llvm.spv.wave.reduce.product.v4f32([[TY1]]) #[[#attr]]
 
 // CHECK: attributes #[[#attr]] = {{{.*}} convergent {{.*}}}

llvm/include/llvm/IR/IntrinsicsSPIRV.td

@@ -125,7 +125,7 @@ def int_spv_rsqrt : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty]
   def int_spv_wave_reduce_min : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>;
   def int_spv_wave_reduce_umin : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>;
   def int_spv_wave_reduce_sum : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>;
-  def int_spv_wave_product : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>;
+  def int_spv_wave_reduce_product : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>;
   def int_spv_wave_is_first_lane : DefaultAttrsIntrinsic<[llvm_i1_ty], [], [IntrConvergent]>;
   def int_spv_wave_readlane : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>, llvm_i32_ty], [IntrConvergent, IntrNoMem]>;
   def int_spv_wave_get_lane_count

llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp

@@ -3569,7 +3569,7 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
     return selectWaveReduceMin(ResVReg, ResType, I, /*IsUnsigned*/ false);
   case Intrinsic::spv_wave_reduce_sum:
     return selectWaveReduceSum(ResVReg, ResType, I);
-  case Intrinsic::spv_wave_product:
+  case Intrinsic::spv_wave_reduce_product:
     return selectWaveReduceProduct(ResVReg, ResType, I);
   case Intrinsic::spv_wave_readlane:
     return selectWaveOpInst(ResVReg, ResType, I,

llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveActiveProduct.ll

@@ -13,29 +13,29 @@
 ; CHECK:   %[[#fexpr:]] = OpFunctionParameter %[[#f32]]
 define float @test_float(float %fexpr) {
 entry:
-; CHECK:   %[[#fret:]] = OpGroupNonUniformFMul %[[#f32]] %[[#scope]] %[[#fexpr]]
-  %0 = call float @llvm.spv.wave.product.f32(float %fexpr)
+; CHECK:   %[[#fret:]] = OpGroupNonUniformFMul %[[#f32]] %[[#scope]] Reduce %[[#fexpr]]
+  %0 = call float @llvm.spv.wave.reduce.product.f32(float %fexpr)
   ret float %0
 }
 
 ; CHECK-LABEL: Begin function test_int
 ; CHECK:   %[[#iexpr:]] = OpFunctionParameter %[[#uint]]
 define i32 @test_int(i32 %iexpr) {
 entry:
-; CHECK:   %[[#iret:]] = OpGroupNonUniformIMul %[[#uint]] %[[#scope]] %[[#iexpr]]
-  %0 = call i32 @llvm.spv.wave.product.i32(i32 %iexpr)
+; CHECK:   %[[#iret:]] = OpGroupNonUniformIMul %[[#uint]] %[[#scope]] Reduce %[[#iexpr]]
+  %0 = call i32 @llvm.spv.wave.reduce.product.i32(i32 %iexpr)
   ret i32 %0
 }
 
 ; CHECK-LABEL: Begin function test_vhalf
 ; CHECK:   %[[#vbexpr:]] = OpFunctionParameter %[[#v4_half]]
 define <4 x half> @test_vhalf(<4 x half> %vbexpr) {
 entry:
-; CHECK:   %[[#vhalfret:]] = OpGroupNonUniformFMul %[[#v4_half]] %[[#scope]] %[[#vbexpr]]
-  %0 = call <4 x half> @llvm.spv.wave.product.v4half(<4 x half> %vbexpr)
+; CHECK:   %[[#vhalfret:]] = OpGroupNonUniformFMul %[[#v4_half]] %[[#scope]] Reduce %[[#vbexpr]]
+  %0 = call <4 x half> @llvm.spv.wave.reduce.product.v4half(<4 x half> %vbexpr)
   ret <4 x half> %0
 }
 
 declare float @llvm.spv.wave.product.f32(float)
 declare i32 @llvm.spv.wave.product.i32(i32)
-declare <4 x half> @llvm.spv.wave.product.v4half(<4 x half>)
+declare <4 x half> @llvm.spv.wave.reduce.product.v4half(<4 x half>)