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slachowskyslachowsky
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[RISCV] Improve 'Zalrsc' atomic load min/max pseudo
There is a shorter instruction sequence possible by leveraging the fact that two sign-extend arguments still order correctly during an unsigned comparison.
1 parent de69a6e commit 7283821

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4 files changed

+30
-74
lines changed

4 files changed

+30
-74
lines changed

‎llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp‎

Lines changed: 3 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -523,17 +523,6 @@ static void insertSext(const RISCVInstrInfo *TII, DebugLoc DL,
523523
.addReg(ShamtReg);
524524
}
525525

526-
static void insertZext(const RISCVInstrInfo *TII, DebugLoc DL,
527-
MachineBasicBlock *MBB, Register ValReg,
528-
Register SrcReg, int64_t Shamt) {
529-
BuildMI(MBB, DL, TII->get(RISCV::SLLI), ValReg)
530-
.addReg(SrcReg)
531-
.addImm(Shamt);
532-
BuildMI(MBB, DL, TII->get(RISCV::SRLI), ValReg)
533-
.addReg(ValReg)
534-
.addImm(Shamt);
535-
}
536-
537526
static void doAtomicMinMaxOpExpansion(const RISCVInstrInfo *TII, MachineInstr &MI,
538527
DebugLoc DL, MachineBasicBlock *ThisMBB,
539528
MachineBasicBlock *LoopHeadMBB,
@@ -546,9 +535,6 @@ static void doAtomicMinMaxOpExpansion(const RISCVInstrInfo *TII, MachineInstr &M
546535
Register ScratchReg = MI.getOperand(1).getReg();
547536
Register AddrReg = MI.getOperand(2).getReg();
548537
Register IncrReg = MI.getOperand(3).getReg();
549-
bool IsUnsigned = BinOp == AtomicRMWInst::UMin ||
550-
BinOp == AtomicRMWInst::UMax;
551-
bool Zext = IsUnsigned && STI->is64Bit() && Width == 32;
552538
AtomicOrdering Ordering =
553539
static_cast<AtomicOrdering>(MI.getOperand(4).getImm());
554540

@@ -558,12 +544,9 @@ static void doAtomicMinMaxOpExpansion(const RISCVInstrInfo *TII, MachineInstr &M
558544
// ifnochangeneeded scratch, incr, .looptail
559545
BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW(Ordering, Width, STI)), DestReg)
560546
.addReg(AddrReg);
561-
if (Zext)
562-
insertZext(TII, DL, LoopHeadMBB, ScratchReg, DestReg, 32);
563-
else
564-
BuildMI(LoopHeadMBB, DL, TII->get(RISCV::ADDI), ScratchReg)
565-
.addReg(DestReg)
566-
.addImm(0);
547+
BuildMI(LoopHeadMBB, DL, TII->get(RISCV::ADDI), ScratchReg)
548+
.addReg(DestReg)
549+
.addImm(0);
567550
switch (BinOp) {
568551
default:
569552
llvm_unreachable("Unexpected AtomicRMW BinOp");

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -24493,10 +24493,9 @@ ISD::NodeType RISCVTargetLowering::getExtendForAtomicRMWArg(unsigned Op) const {
2449324493
switch (Op) {
2449424494
case ISD::ATOMIC_LOAD_MIN:
2449524495
case ISD::ATOMIC_LOAD_MAX:
24496-
return ISD::SIGN_EXTEND;
2449724496
case ISD::ATOMIC_LOAD_UMIN:
2449824497
case ISD::ATOMIC_LOAD_UMAX:
24499-
return ISD::ZERO_EXTEND;
24498+
return ISD::SIGN_EXTEND;
2450024499
default:
2450124500
break;
2450224501
}

‎llvm/test/CodeGen/RISCV/atomic-rmw.ll‎

Lines changed: 20 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -36173,12 +36173,10 @@ define i32 @atomicrmw_umax_i32_monotonic(ptr %a, i32 %b) nounwind {
3617336173
;
3617436174
; RV64I-ZALRSC-LABEL: atomicrmw_umax_i32_monotonic:
3617536175
; RV64I-ZALRSC: # %bb.0:
36176-
; RV64I-ZALRSC-NEXT: slli a1, a1, 32
36177-
; RV64I-ZALRSC-NEXT: srli a2, a1, 32
36176+
; RV64I-ZALRSC-NEXT: sext.w a2, a1
3617836177
; RV64I-ZALRSC-NEXT: .LBB175_1: # =>This Inner Loop Header: Depth=1
3617936178
; RV64I-ZALRSC-NEXT: lr.w a1, (a0)
36180-
; RV64I-ZALRSC-NEXT: slli a3, a1, 32
36181-
; RV64I-ZALRSC-NEXT: srli a3, a3, 32
36179+
; RV64I-ZALRSC-NEXT: mv a3, a1
3618236180
; RV64I-ZALRSC-NEXT: bgeu a3, a2, .LBB175_3
3618336181
; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB175_1 Depth=1
3618436182
; RV64I-ZALRSC-NEXT: mv a3, a2
@@ -36300,12 +36298,10 @@ define i32 @atomicrmw_umax_i32_acquire(ptr %a, i32 %b) nounwind {
3630036298
;
3630136299
; RV64I-ZALRSC-LABEL: atomicrmw_umax_i32_acquire:
3630236300
; RV64I-ZALRSC: # %bb.0:
36303-
; RV64I-ZALRSC-NEXT: slli a1, a1, 32
36304-
; RV64I-ZALRSC-NEXT: srli a2, a1, 32
36301+
; RV64I-ZALRSC-NEXT: sext.w a2, a1
3630536302
; RV64I-ZALRSC-NEXT: .LBB176_1: # =>This Inner Loop Header: Depth=1
3630636303
; RV64I-ZALRSC-NEXT: lr.w.aq a1, (a0)
36307-
; RV64I-ZALRSC-NEXT: slli a3, a1, 32
36308-
; RV64I-ZALRSC-NEXT: srli a3, a3, 32
36304+
; RV64I-ZALRSC-NEXT: mv a3, a1
3630936305
; RV64I-ZALRSC-NEXT: bgeu a3, a2, .LBB176_3
3631036306
; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB176_1 Depth=1
3631136307
; RV64I-ZALRSC-NEXT: mv a3, a2
@@ -36432,12 +36428,10 @@ define i32 @atomicrmw_umax_i32_release(ptr %a, i32 %b) nounwind {
3643236428
;
3643336429
; RV64I-ZALRSC-LABEL: atomicrmw_umax_i32_release:
3643436430
; RV64I-ZALRSC: # %bb.0:
36435-
; RV64I-ZALRSC-NEXT: slli a1, a1, 32
36436-
; RV64I-ZALRSC-NEXT: srli a2, a1, 32
36431+
; RV64I-ZALRSC-NEXT: sext.w a2, a1
3643736432
; RV64I-ZALRSC-NEXT: .LBB177_1: # =>This Inner Loop Header: Depth=1
3643836433
; RV64I-ZALRSC-NEXT: lr.w a1, (a0)
36439-
; RV64I-ZALRSC-NEXT: slli a3, a1, 32
36440-
; RV64I-ZALRSC-NEXT: srli a3, a3, 32
36434+
; RV64I-ZALRSC-NEXT: mv a3, a1
3644136435
; RV64I-ZALRSC-NEXT: bgeu a3, a2, .LBB177_3
3644236436
; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB177_1 Depth=1
3644336437
; RV64I-ZALRSC-NEXT: mv a3, a2
@@ -36564,12 +36558,10 @@ define i32 @atomicrmw_umax_i32_acq_rel(ptr %a, i32 %b) nounwind {
3656436558
;
3656536559
; RV64I-ZALRSC-LABEL: atomicrmw_umax_i32_acq_rel:
3656636560
; RV64I-ZALRSC: # %bb.0:
36567-
; RV64I-ZALRSC-NEXT: slli a1, a1, 32
36568-
; RV64I-ZALRSC-NEXT: srli a2, a1, 32
36561+
; RV64I-ZALRSC-NEXT: sext.w a2, a1
3656936562
; RV64I-ZALRSC-NEXT: .LBB178_1: # =>This Inner Loop Header: Depth=1
3657036563
; RV64I-ZALRSC-NEXT: lr.w.aq a1, (a0)
36571-
; RV64I-ZALRSC-NEXT: slli a3, a1, 32
36572-
; RV64I-ZALRSC-NEXT: srli a3, a3, 32
36564+
; RV64I-ZALRSC-NEXT: mv a3, a1
3657336565
; RV64I-ZALRSC-NEXT: bgeu a3, a2, .LBB178_3
3657436566
; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB178_1 Depth=1
3657536567
; RV64I-ZALRSC-NEXT: mv a3, a2
@@ -36696,12 +36688,10 @@ define i32 @atomicrmw_umax_i32_seq_cst(ptr %a, i32 %b) nounwind {
3669636688
;
3669736689
; RV64I-ZALRSC-LABEL: atomicrmw_umax_i32_seq_cst:
3669836690
; RV64I-ZALRSC: # %bb.0:
36699-
; RV64I-ZALRSC-NEXT: slli a1, a1, 32
36700-
; RV64I-ZALRSC-NEXT: srli a2, a1, 32
36691+
; RV64I-ZALRSC-NEXT: sext.w a2, a1
3670136692
; RV64I-ZALRSC-NEXT: .LBB179_1: # =>This Inner Loop Header: Depth=1
3670236693
; RV64I-ZALRSC-NEXT: lr.w.aqrl a1, (a0)
36703-
; RV64I-ZALRSC-NEXT: slli a3, a1, 32
36704-
; RV64I-ZALRSC-NEXT: srli a3, a3, 32
36694+
; RV64I-ZALRSC-NEXT: mv a3, a1
3670536695
; RV64I-ZALRSC-NEXT: bgeu a3, a2, .LBB179_3
3670636696
; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB179_1 Depth=1
3670736697
; RV64I-ZALRSC-NEXT: mv a3, a2
@@ -36823,12 +36813,10 @@ define i32 @atomicrmw_umin_i32_monotonic(ptr %a, i32 %b) nounwind {
3682336813
;
3682436814
; RV64I-ZALRSC-LABEL: atomicrmw_umin_i32_monotonic:
3682536815
; RV64I-ZALRSC: # %bb.0:
36826-
; RV64I-ZALRSC-NEXT: slli a1, a1, 32
36827-
; RV64I-ZALRSC-NEXT: srli a2, a1, 32
36816+
; RV64I-ZALRSC-NEXT: sext.w a2, a1
3682836817
; RV64I-ZALRSC-NEXT: .LBB180_1: # =>This Inner Loop Header: Depth=1
3682936818
; RV64I-ZALRSC-NEXT: lr.w a1, (a0)
36830-
; RV64I-ZALRSC-NEXT: slli a3, a1, 32
36831-
; RV64I-ZALRSC-NEXT: srli a3, a3, 32
36819+
; RV64I-ZALRSC-NEXT: mv a3, a1
3683236820
; RV64I-ZALRSC-NEXT: bgeu a2, a3, .LBB180_3
3683336821
; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB180_1 Depth=1
3683436822
; RV64I-ZALRSC-NEXT: mv a3, a2
@@ -36950,12 +36938,10 @@ define i32 @atomicrmw_umin_i32_acquire(ptr %a, i32 %b) nounwind {
3695036938
;
3695136939
; RV64I-ZALRSC-LABEL: atomicrmw_umin_i32_acquire:
3695236940
; RV64I-ZALRSC: # %bb.0:
36953-
; RV64I-ZALRSC-NEXT: slli a1, a1, 32
36954-
; RV64I-ZALRSC-NEXT: srli a2, a1, 32
36941+
; RV64I-ZALRSC-NEXT: sext.w a2, a1
3695536942
; RV64I-ZALRSC-NEXT: .LBB181_1: # =>This Inner Loop Header: Depth=1
3695636943
; RV64I-ZALRSC-NEXT: lr.w.aq a1, (a0)
36957-
; RV64I-ZALRSC-NEXT: slli a3, a1, 32
36958-
; RV64I-ZALRSC-NEXT: srli a3, a3, 32
36944+
; RV64I-ZALRSC-NEXT: mv a3, a1
3695936945
; RV64I-ZALRSC-NEXT: bgeu a2, a3, .LBB181_3
3696036946
; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB181_1 Depth=1
3696136947
; RV64I-ZALRSC-NEXT: mv a3, a2
@@ -37082,12 +37068,10 @@ define i32 @atomicrmw_umin_i32_release(ptr %a, i32 %b) nounwind {
3708237068
;
3708337069
; RV64I-ZALRSC-LABEL: atomicrmw_umin_i32_release:
3708437070
; RV64I-ZALRSC: # %bb.0:
37085-
; RV64I-ZALRSC-NEXT: slli a1, a1, 32
37086-
; RV64I-ZALRSC-NEXT: srli a2, a1, 32
37071+
; RV64I-ZALRSC-NEXT: sext.w a2, a1
3708737072
; RV64I-ZALRSC-NEXT: .LBB182_1: # =>This Inner Loop Header: Depth=1
3708837073
; RV64I-ZALRSC-NEXT: lr.w a1, (a0)
37089-
; RV64I-ZALRSC-NEXT: slli a3, a1, 32
37090-
; RV64I-ZALRSC-NEXT: srli a3, a3, 32
37074+
; RV64I-ZALRSC-NEXT: mv a3, a1
3709137075
; RV64I-ZALRSC-NEXT: bgeu a2, a3, .LBB182_3
3709237076
; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB182_1 Depth=1
3709337077
; RV64I-ZALRSC-NEXT: mv a3, a2
@@ -37214,12 +37198,10 @@ define i32 @atomicrmw_umin_i32_acq_rel(ptr %a, i32 %b) nounwind {
3721437198
;
3721537199
; RV64I-ZALRSC-LABEL: atomicrmw_umin_i32_acq_rel:
3721637200
; RV64I-ZALRSC: # %bb.0:
37217-
; RV64I-ZALRSC-NEXT: slli a1, a1, 32
37218-
; RV64I-ZALRSC-NEXT: srli a2, a1, 32
37201+
; RV64I-ZALRSC-NEXT: sext.w a2, a1
3721937202
; RV64I-ZALRSC-NEXT: .LBB183_1: # =>This Inner Loop Header: Depth=1
3722037203
; RV64I-ZALRSC-NEXT: lr.w.aq a1, (a0)
37221-
; RV64I-ZALRSC-NEXT: slli a3, a1, 32
37222-
; RV64I-ZALRSC-NEXT: srli a3, a3, 32
37204+
; RV64I-ZALRSC-NEXT: mv a3, a1
3722337205
; RV64I-ZALRSC-NEXT: bgeu a2, a3, .LBB183_3
3722437206
; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB183_1 Depth=1
3722537207
; RV64I-ZALRSC-NEXT: mv a3, a2
@@ -37346,12 +37328,10 @@ define i32 @atomicrmw_umin_i32_seq_cst(ptr %a, i32 %b) nounwind {
3734637328
;
3734737329
; RV64I-ZALRSC-LABEL: atomicrmw_umin_i32_seq_cst:
3734837330
; RV64I-ZALRSC: # %bb.0:
37349-
; RV64I-ZALRSC-NEXT: slli a1, a1, 32
37350-
; RV64I-ZALRSC-NEXT: srli a2, a1, 32
37331+
; RV64I-ZALRSC-NEXT: sext.w a2, a1
3735137332
; RV64I-ZALRSC-NEXT: .LBB184_1: # =>This Inner Loop Header: Depth=1
3735237333
; RV64I-ZALRSC-NEXT: lr.w.aqrl a1, (a0)
37353-
; RV64I-ZALRSC-NEXT: slli a3, a1, 32
37354-
; RV64I-ZALRSC-NEXT: srli a3, a3, 32
37334+
; RV64I-ZALRSC-NEXT: mv a3, a1
3735537335
; RV64I-ZALRSC-NEXT: bgeu a2, a3, .LBB184_3
3735637336
; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB184_1 Depth=1
3735737337
; RV64I-ZALRSC-NEXT: mv a3, a2

‎llvm/test/CodeGen/RISCV/atomic-signext.ll‎

Lines changed: 6 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -4114,12 +4114,10 @@ define signext i32 @atomicrmw_umax_i32_monotonic(ptr %a, i32 %b) nounwind {
41144114
;
41154115
; RV64I-ZALRSC-LABEL: atomicrmw_umax_i32_monotonic:
41164116
; RV64I-ZALRSC: # %bb.0:
4117-
; RV64I-ZALRSC-NEXT: slli a1, a1, 32
4118-
; RV64I-ZALRSC-NEXT: srli a2, a1, 32
4117+
; RV64I-ZALRSC-NEXT: sext.w a2, a1
41194118
; RV64I-ZALRSC-NEXT: .LBB34_1: # =>This Inner Loop Header: Depth=1
41204119
; RV64I-ZALRSC-NEXT: lr.w a1, (a0)
4121-
; RV64I-ZALRSC-NEXT: slli a3, a1, 32
4122-
; RV64I-ZALRSC-NEXT: srli a3, a3, 32
4120+
; RV64I-ZALRSC-NEXT: mv a3, a1
41234121
; RV64I-ZALRSC-NEXT: bgeu a3, a2, .LBB34_3
41244122
; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB34_1 Depth=1
41254123
; RV64I-ZALRSC-NEXT: mv a3, a2
@@ -4236,12 +4234,10 @@ define signext i32 @atomicrmw_umin_i32_monotonic(ptr %a, i32 %b) nounwind {
42364234
;
42374235
; RV64I-ZALRSC-LABEL: atomicrmw_umin_i32_monotonic:
42384236
; RV64I-ZALRSC: # %bb.0:
4239-
; RV64I-ZALRSC-NEXT: slli a1, a1, 32
4240-
; RV64I-ZALRSC-NEXT: srli a2, a1, 32
4237+
; RV64I-ZALRSC-NEXT: sext.w a2, a1
42414238
; RV64I-ZALRSC-NEXT: .LBB35_1: # =>This Inner Loop Header: Depth=1
42424239
; RV64I-ZALRSC-NEXT: lr.w a1, (a0)
4243-
; RV64I-ZALRSC-NEXT: slli a3, a1, 32
4244-
; RV64I-ZALRSC-NEXT: srli a3, a3, 32
4240+
; RV64I-ZALRSC-NEXT: mv a3, a1
42454241
; RV64I-ZALRSC-NEXT: bgeu a2, a3, .LBB35_3
42464242
; RV64I-ZALRSC-NEXT: # %bb.2: # in Loop: Header=BB35_1 Depth=1
42474243
; RV64I-ZALRSC-NEXT: mv a3, a2
@@ -7873,8 +7869,7 @@ define signext i32 @atomicrmw_umax_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
78737869
; RV64I-ZALRSC-NEXT: .LBB62_3: # %then
78747870
; RV64I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
78757871
; RV64I-ZALRSC-NEXT: lr.w a1, (a0)
7876-
; RV64I-ZALRSC-NEXT: slli a3, a1, 32
7877-
; RV64I-ZALRSC-NEXT: srli a3, a3, 32
7872+
; RV64I-ZALRSC-NEXT: mv a3, a1
78787873
; RV64I-ZALRSC-NEXT: bgeu a3, a2, .LBB62_5
78797874
; RV64I-ZALRSC-NEXT: # %bb.4: # %then
78807875
; RV64I-ZALRSC-NEXT: # in Loop: Header=BB62_3 Depth=1
@@ -8090,8 +8085,7 @@ define signext i32 @atomicrmw_umin_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
80908085
; RV64I-ZALRSC-NEXT: .LBB63_5: # %then
80918086
; RV64I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1
80928087
; RV64I-ZALRSC-NEXT: lr.w a0, (a1)
8093-
; RV64I-ZALRSC-NEXT: slli a3, a0, 32
8094-
; RV64I-ZALRSC-NEXT: srli a3, a3, 32
8088+
; RV64I-ZALRSC-NEXT: mv a3, a0
80958089
; RV64I-ZALRSC-NEXT: bgeu a2, a3, .LBB63_7
80968090
; RV64I-ZALRSC-NEXT: # %bb.6: # %then
80978091
; RV64I-ZALRSC-NEXT: # in Loop: Header=BB63_5 Depth=1

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