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jrbyrnesjrbyrnes
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[RegisterCoalescer]: Try inflated RC for coalescing reg->subreg
Change-Id: Id1123431e9fdcabac2811f5b18abff7d66e2d1f3
1 parent d41f2d4 commit 72a9bfb

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7 files changed

+2568
-1893
lines changed

7 files changed

+2568
-1893
lines changed

‎llvm/include/llvm/CodeGen/MachineRegisterInfo.h‎

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -738,7 +738,14 @@ class MachineRegisterInfo {
738738

739739
/// recomputeRegClass - Try to find a legal super-class of Reg's register
740740
/// class that still satisfies the constraints from the instructions using
741-
/// Reg. Returns true if Reg was upgraded.
741+
/// \p Reg. \p return the super-class TargetRegisterClass if one was found,
742+
/// otherwise \p return the original TargetRegisterClass.
743+
const TargetRegisterClass *
744+
getLargestConstrainedSuperClass(Register Reg) const;
745+
746+
/// recomputeRegClass - Try to find a legal super-class of Reg's register
747+
/// class that still satisfies the constraints from the instructions using
748+
/// \p Reg. \p return true if Reg was upgraded.
742749
///
743750
/// This method can be used after constraints have been removed from a
744751
/// virtual register, for example after removing instructions or splitting

‎llvm/lib/CodeGen/MachineRegisterInfo.cpp‎

Lines changed: 12 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -118,16 +118,16 @@ MachineRegisterInfo::constrainRegAttrs(Register Reg,
118118
return true;
119119
}
120120

121-
bool
122-
MachineRegisterInfo::recomputeRegClass(Register Reg) {
121+
const TargetRegisterClass *
122+
MachineRegisterInfo::getLargestConstrainedSuperClass(Register Reg) const {
123123
const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
124124
const TargetRegisterClass *OldRC = getRegClass(Reg);
125125
const TargetRegisterInfo *TRI = getTargetRegisterInfo();
126126
const TargetRegisterClass *NewRC = TRI->getLargestLegalSuperClass(OldRC, *MF);
127127

128128
// Stop early if there is no room to grow.
129129
if (NewRC == OldRC)
130-
return false;
130+
return NewRC;
131131

132132
// Accumulate constraints from all uses.
133133
for (MachineOperand &MO : reg_nodbg_operands(Reg)) {
@@ -136,8 +136,16 @@ MachineRegisterInfo::recomputeRegClass(Register Reg) {
136136
unsigned OpNo = &MO - &MI->getOperand(0);
137137
NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII, TRI);
138138
if (!NewRC || NewRC == OldRC)
139-
return false;
139+
return OldRC;
140140
}
141+
return NewRC;
142+
}
143+
144+
bool MachineRegisterInfo::recomputeRegClass(Register Reg) {
145+
const TargetRegisterClass *OldRC = getRegClass(Reg);
146+
const TargetRegisterClass *NewRC = getLargestConstrainedSuperClass(Reg);
147+
if (NewRC == OldRC)
148+
return false;
141149
setRegClass(Reg, NewRC);
142150
return true;
143151
}

‎llvm/lib/CodeGen/RegisterCoalescer.cpp‎

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -477,7 +477,9 @@ bool CoalescerPair::setRegisters(const MachineInstr *MI) {
477477
Flipped = true;
478478
}
479479

480-
const MachineRegisterInfo &MRI = MI->getMF()->getRegInfo();
480+
const MachineFunction *MF = MI->getMF();
481+
482+
const MachineRegisterInfo &MRI = MF->getRegInfo();
481483
const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
482484

483485
if (Dst.isPhysical()) {
@@ -515,6 +517,11 @@ bool CoalescerPair::setRegisters(const MachineInstr *MI) {
515517
// SrcReg will be merged with a sub-register of DstReg.
516518
SrcIdx = DstSub;
517519
NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub);
520+
if (!NewRC) {
521+
auto SuperDstRC = MRI.getLargestConstrainedSuperClass(Dst);
522+
if (SuperDstRC != DstRC)
523+
NewRC = TRI.getMatchingSuperRegClass(SuperDstRC, SrcRC, DstSub);
524+
}
518525
} else if (SrcSub) {
519526
// DstReg will be merged with a sub-register of SrcReg.
520527
DstIdx = SrcSub;

‎llvm/test/CodeGen/AMDGPU/coalesce-copy-to-agpr-to-av-registers.mir‎

Lines changed: 63 additions & 92 deletions
Original file line numberDiff line numberDiff line change
@@ -1148,10 +1148,10 @@ body: |
11481148
; CHECK-LABEL: name: copy_vgpr32_vgpr64_to_areg96_coalesce_with_av96
11491149
; CHECK: liveins: $vgpr0, $vgpr1_vgpr2
11501150
; CHECK-NEXT: {{ $}}
1151-
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
1152-
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr1_vgpr2
1153-
; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0:areg_96 = COPY [[COPY]]
1154-
; CHECK-NEXT: [[COPY2:%[0-9]+]].sub1_sub2:areg_96 = COPY [[COPY1]]
1151+
; CHECK-NEXT: [[COPY:%[0-9]+]].sub0:vreg_96 = COPY $vgpr0
1152+
; CHECK-NEXT: [[COPY:%[0-9]+]].sub1_sub2:vreg_96 = COPY $vgpr1_vgpr2
1153+
; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0:areg_96 = COPY [[COPY]].sub2
1154+
; CHECK-NEXT: [[COPY2:%[0-9]+]].sub1_sub2:areg_96 = COPY [[COPY]].sub0_sub1
11551155
; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4587529 /* reguse:AReg_96 */, [[COPY2]]
11561156
; CHECK-NEXT: SI_RETURN
11571157
undef %0.sub0:vreg_96 = COPY $vgpr0
@@ -1442,11 +1442,9 @@ body: |
14421442
; CHECK-LABEL: name: copy_vgpr32_to_areg64_coalesce_with_av64_snop
14431443
; CHECK: liveins: $vgpr0, $vgpr1
14441444
; CHECK-NEXT: {{ $}}
1445-
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
1446-
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
1447-
; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0:areg_64 = COPY [[COPY]]
1448-
; CHECK-NEXT: [[COPY2:%[0-9]+]].sub1:areg_64 = COPY [[COPY1]]
1449-
; CHECK-NEXT: S_NOP 0, implicit [[COPY2]]
1445+
; CHECK-NEXT: undef [[COPY:%[0-9]+]].sub0:av_64 = COPY $vgpr0
1446+
; CHECK-NEXT: [[COPY:%[0-9]+]].sub1:av_64 = COPY $vgpr1
1447+
; CHECK-NEXT: S_NOP 0, implicit [[COPY]]
14501448
; CHECK-NEXT: SI_RETURN
14511449
%0:vgpr_32 = COPY $vgpr0
14521450
%1:vgpr_32 = COPY $vgpr1
@@ -1467,11 +1465,9 @@ body: |
14671465
; CHECK-LABEL: name: copy_vgpr32_to_areg64_align2_coalesce_with_av64_align2_snop
14681466
; CHECK: liveins: $vgpr0, $vgpr1
14691467
; CHECK-NEXT: {{ $}}
1470-
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
1471-
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
1472-
; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0:areg_64_align2 = COPY [[COPY]]
1473-
; CHECK-NEXT: [[COPY2:%[0-9]+]].sub1:areg_64_align2 = COPY [[COPY1]]
1474-
; CHECK-NEXT: S_NOP 0, implicit [[COPY2]]
1468+
; CHECK-NEXT: undef [[COPY:%[0-9]+]].sub0:av_64_align2 = COPY $vgpr0
1469+
; CHECK-NEXT: [[COPY:%[0-9]+]].sub1:av_64_align2 = COPY $vgpr1
1470+
; CHECK-NEXT: S_NOP 0, implicit [[COPY]]
14751471
; CHECK-NEXT: SI_RETURN
14761472
%0:vgpr_32 = COPY $vgpr0
14771473
%1:vgpr_32 = COPY $vgpr1
@@ -1492,13 +1488,10 @@ body: |
14921488
; CHECK-LABEL: name: copy_vgpr32_to_areg96_coalesce_with_av96_snop
14931489
; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
14941490
; CHECK-NEXT: {{ $}}
1495-
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
1496-
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
1497-
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
1498-
; CHECK-NEXT: undef [[COPY3:%[0-9]+]].sub0:areg_96 = COPY [[COPY]]
1499-
; CHECK-NEXT: [[COPY3:%[0-9]+]].sub1:areg_96 = COPY [[COPY1]]
1500-
; CHECK-NEXT: [[COPY3:%[0-9]+]].sub2:areg_96 = COPY [[COPY2]]
1501-
; CHECK-NEXT: S_NOP 0, implicit [[COPY3]]
1491+
; CHECK-NEXT: undef [[COPY:%[0-9]+]].sub0:av_96 = COPY $vgpr0
1492+
; CHECK-NEXT: [[COPY:%[0-9]+]].sub1:av_96 = COPY $vgpr1
1493+
; CHECK-NEXT: [[COPY:%[0-9]+]].sub2:av_96 = COPY $vgpr2
1494+
; CHECK-NEXT: S_NOP 0, implicit [[COPY]]
15021495
; CHECK-NEXT: SI_RETURN
15031496
%0:vgpr_32 = COPY $vgpr0
15041497
%1:vgpr_32 = COPY $vgpr1
@@ -1521,13 +1514,10 @@ body: |
15211514
; CHECK-LABEL: name: copy_vgpr32_to_areg96_coalesce_with_av96_align2_snop
15221515
; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
15231516
; CHECK-NEXT: {{ $}}
1524-
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
1525-
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
1526-
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
1527-
; CHECK-NEXT: undef [[COPY3:%[0-9]+]].sub0:areg_96_align2 = COPY [[COPY]]
1528-
; CHECK-NEXT: [[COPY3:%[0-9]+]].sub1:areg_96_align2 = COPY [[COPY1]]
1529-
; CHECK-NEXT: [[COPY3:%[0-9]+]].sub2:areg_96_align2 = COPY [[COPY2]]
1530-
; CHECK-NEXT: S_NOP 0, implicit [[COPY3]]
1517+
; CHECK-NEXT: undef [[COPY:%[0-9]+]].sub0:av_96_align2 = COPY $vgpr0
1518+
; CHECK-NEXT: [[COPY:%[0-9]+]].sub1:av_96_align2 = COPY $vgpr1
1519+
; CHECK-NEXT: [[COPY:%[0-9]+]].sub2:av_96_align2 = COPY $vgpr2
1520+
; CHECK-NEXT: S_NOP 0, implicit [[COPY]]
15311521
; CHECK-NEXT: SI_RETURN
15321522
%0:vgpr_32 = COPY $vgpr0
15331523
%1:vgpr_32 = COPY $vgpr1
@@ -1550,11 +1540,9 @@ body: |
15501540
; CHECK-LABEL: name: copy_vgpr64_to_areg64_coalesce_with_av128_snop
15511541
; CHECK: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
15521542
; CHECK-NEXT: {{ $}}
1553-
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
1554-
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
1555-
; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0_sub1:areg_128 = COPY [[COPY]]
1556-
; CHECK-NEXT: [[COPY2:%[0-9]+]].sub2_sub3:areg_128 = COPY [[COPY1]]
1557-
; CHECK-NEXT: S_NOP 0, implicit [[COPY2]]
1543+
; CHECK-NEXT: undef [[COPY:%[0-9]+]].sub0_sub1:av_128 = COPY $vgpr0_vgpr1
1544+
; CHECK-NEXT: [[COPY:%[0-9]+]].sub2_sub3:av_128 = COPY $vgpr2_vgpr3
1545+
; CHECK-NEXT: S_NOP 0, implicit [[COPY]]
15581546
; CHECK-NEXT: SI_RETURN
15591547
%0:vreg_64 = COPY $vgpr0_vgpr1
15601548
%1:vreg_64 = COPY $vgpr2_vgpr3
@@ -1575,11 +1563,9 @@ body: |
15751563
; CHECK-LABEL: name: copy_vgpr64_to_areg64_align2_coalesce_with_av128_align2_snop
15761564
; CHECK: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
15771565
; CHECK-NEXT: {{ $}}
1578-
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
1579-
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
1580-
; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0_sub1:areg_128_align2 = COPY [[COPY]]
1581-
; CHECK-NEXT: [[COPY2:%[0-9]+]].sub2_sub3:areg_128_align2 = COPY [[COPY1]]
1582-
; CHECK-NEXT: S_NOP 0, implicit [[COPY2]]
1566+
; CHECK-NEXT: undef [[COPY:%[0-9]+]].sub0_sub1:av_128_align2 = COPY $vgpr0_vgpr1
1567+
; CHECK-NEXT: [[COPY:%[0-9]+]].sub2_sub3:av_128_align2 = COPY $vgpr2_vgpr3
1568+
; CHECK-NEXT: S_NOP 0, implicit [[COPY]]
15831569
; CHECK-NEXT: SI_RETURN
15841570
%0:vreg_64 = COPY $vgpr0_vgpr1
15851571
%1:vreg_64 = COPY $vgpr2_vgpr3
@@ -1625,11 +1611,9 @@ body: |
16251611
; CHECK-LABEL: name: copy_vgpr32_vgpr64_to_areg96_coalesce_with_av96_snop
16261612
; CHECK: liveins: $vgpr0, $vgpr1_vgpr2
16271613
; CHECK-NEXT: {{ $}}
1628-
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
1629-
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr1_vgpr2
1630-
; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0:areg_96 = COPY [[COPY]]
1631-
; CHECK-NEXT: [[COPY2:%[0-9]+]].sub1_sub2:areg_96 = COPY [[COPY1]]
1632-
; CHECK-NEXT: S_NOP 0, implicit [[COPY2]]
1614+
; CHECK-NEXT: undef [[COPY:%[0-9]+]].sub0:av_96 = COPY $vgpr0
1615+
; CHECK-NEXT: [[COPY:%[0-9]+]].sub1_sub2:av_96 = COPY $vgpr1_vgpr2
1616+
; CHECK-NEXT: S_NOP 0, implicit [[COPY]]
16331617
; CHECK-NEXT: SI_RETURN
16341618
%0:vgpr_32 = COPY $vgpr0
16351619
%1:vreg_64 = COPY $vgpr1_vgpr2
@@ -1650,11 +1634,9 @@ body: |
16501634
; CHECK-LABEL: name: copy_vgpr32_vgpr64_to_areg96_coalesce_with_av96_align2_snop
16511635
; CHECK: liveins: $vgpr0, $vgpr1_vgpr2
16521636
; CHECK-NEXT: {{ $}}
1653-
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
1654-
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr1_vgpr2
1655-
; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0:areg_96_align2 = COPY [[COPY]]
1656-
; CHECK-NEXT: [[COPY2:%[0-9]+]].sub1_sub2:areg_96_align2 = COPY [[COPY1]]
1657-
; CHECK-NEXT: S_NOP 0, implicit [[COPY2]]
1637+
; CHECK-NEXT: undef [[COPY:%[0-9]+]].sub0:av_96_align2 = COPY $vgpr0
1638+
; CHECK-NEXT: [[COPY:%[0-9]+]].sub1_sub2:av_96_align2 = COPY $vgpr1_vgpr2
1639+
; CHECK-NEXT: S_NOP 0, implicit [[COPY]]
16581640
; CHECK-NEXT: SI_RETURN
16591641
%0:vgpr_32 = COPY $vgpr0
16601642
%1:vreg_64 = COPY $vgpr1_vgpr2
@@ -1675,11 +1657,9 @@ body: |
16751657
; CHECK-LABEL: name: copy_vgpr64_vgpr32_to_areg96_coalesce_with_av96_snop
16761658
; CHECK: liveins: $vgpr0_vgpr1, $vgpr2
16771659
; CHECK-NEXT: {{ $}}
1678-
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
1679-
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
1680-
; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0_sub1:areg_96 = COPY [[COPY]]
1681-
; CHECK-NEXT: [[COPY2:%[0-9]+]].sub2:areg_96 = COPY [[COPY1]]
1682-
; CHECK-NEXT: S_NOP 0, implicit [[COPY2]]
1660+
; CHECK-NEXT: undef [[COPY:%[0-9]+]].sub0_sub1:av_96 = COPY $vgpr0_vgpr1
1661+
; CHECK-NEXT: [[COPY:%[0-9]+]].sub2:av_96 = COPY $vgpr2
1662+
; CHECK-NEXT: S_NOP 0, implicit [[COPY]]
16831663
; CHECK-NEXT: SI_RETURN
16841664
%0:vreg_64 = COPY $vgpr0_vgpr1
16851665
%1:vgpr_32 = COPY $vgpr2
@@ -1700,11 +1680,9 @@ body: |
17001680
; CHECK-LABEL: name: copy_vgpr64_vgpr32_to_areg96_coalesce_with_av96_align2_snop
17011681
; CHECK: liveins: $vgpr0, $vgpr1_vgpr2
17021682
; CHECK-NEXT: {{ $}}
1703-
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
1704-
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
1705-
; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0_sub1:areg_96_align2 = COPY [[COPY]]
1706-
; CHECK-NEXT: [[COPY2:%[0-9]+]].sub2:areg_96_align2 = COPY [[COPY1]]
1707-
; CHECK-NEXT: S_NOP 0, implicit [[COPY2]]
1683+
; CHECK-NEXT: undef [[COPY:%[0-9]+]].sub0_sub1:av_96_align2 = COPY $vgpr0_vgpr1
1684+
; CHECK-NEXT: [[COPY:%[0-9]+]].sub2:av_96_align2 = COPY $vgpr2
1685+
; CHECK-NEXT: S_NOP 0, implicit [[COPY]]
17081686
; CHECK-NEXT: SI_RETURN
17091687
%0:vreg_64 = COPY $vgpr0_vgpr1
17101688
%1:vgpr_32 = COPY $vgpr2
@@ -1725,10 +1703,9 @@ body: |
17251703
; CHECK-LABEL: name: copy_vgpr32_x2_to_areg64_snop
17261704
; CHECK: liveins: $vgpr0
17271705
; CHECK-NEXT: {{ $}}
1728-
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
1729-
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_64 = COPY [[COPY]]
1730-
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_64 = COPY [[COPY]]
1731-
; CHECK-NEXT: S_NOP 0, implicit [[COPY1]]
1706+
; CHECK-NEXT: undef [[COPY:%[0-9]+]].sub0:av_64 = COPY $vgpr0
1707+
; CHECK-NEXT: [[COPY:%[0-9]+]].sub1:av_64 = COPY [[COPY]].sub0
1708+
; CHECK-NEXT: S_NOP 0, implicit [[COPY]]
17321709
; CHECK-NEXT: SI_RETURN
17331710
%0:vgpr_32 = COPY $vgpr0
17341711
undef %2.sub0:areg_64 = COPY %0
@@ -1748,11 +1725,9 @@ body: |
17481725
; CHECK-LABEL: name: copy_vgpr32_x2_to_areg64_coalesce_with_av64_align2_snop
17491726
; CHECK: liveins: $vgpr0, $vgpr1
17501727
; CHECK-NEXT: {{ $}}
1751-
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
1752-
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
1753-
; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0:areg_64_align2 = COPY [[COPY]]
1754-
; CHECK-NEXT: [[COPY2:%[0-9]+]].sub1:areg_64_align2 = COPY [[COPY1]]
1755-
; CHECK-NEXT: S_NOP 0, implicit [[COPY2]]
1728+
; CHECK-NEXT: undef [[COPY:%[0-9]+]].sub0:av_64_align2 = COPY $vgpr0
1729+
; CHECK-NEXT: [[COPY:%[0-9]+]].sub1:av_64_align2 = COPY $vgpr1
1730+
; CHECK-NEXT: S_NOP 0, implicit [[COPY]]
17561731
; CHECK-NEXT: SI_RETURN
17571732
%0:vgpr_32 = COPY $vgpr0
17581733
%1:vgpr_32 = COPY $vgpr1
@@ -1773,10 +1748,9 @@ body: |
17731748
; CHECK-LABEL: name: copy_vgpr32_x3_to_areg96_snop
17741749
; CHECK: liveins: $vgpr0
17751750
; CHECK-NEXT: {{ $}}
1776-
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
1777-
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_96 = COPY [[COPY]]
1778-
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_96 = COPY [[COPY]]
1779-
; CHECK-NEXT: S_NOP 0, implicit [[COPY1]]
1751+
; CHECK-NEXT: undef [[COPY:%[0-9]+]].sub0:av_96 = COPY $vgpr0
1752+
; CHECK-NEXT: [[COPY:%[0-9]+]].sub1:av_96 = COPY [[COPY]].sub0
1753+
; CHECK-NEXT: S_NOP 0, implicit [[COPY]]
17801754
; CHECK-NEXT: SI_RETURN
17811755
%0:vgpr_32 = COPY $vgpr0
17821756
undef %1.sub0:areg_96 = COPY %0
@@ -1796,10 +1770,9 @@ body: |
17961770
; CHECK-LABEL: name: copy_vgpr32_x3_to_areg96_align2_snop
17971771
; CHECK: liveins: $vgpr0
17981772
; CHECK-NEXT: {{ $}}
1799-
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
1800-
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_96_align2 = COPY [[COPY]]
1801-
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_96_align2 = COPY [[COPY]]
1802-
; CHECK-NEXT: S_NOP 0, implicit [[COPY1]]
1773+
; CHECK-NEXT: undef [[COPY:%[0-9]+]].sub0:av_96_align2 = COPY $vgpr0
1774+
; CHECK-NEXT: [[COPY:%[0-9]+]].sub1:av_96_align2 = COPY [[COPY]].sub0
1775+
; CHECK-NEXT: S_NOP 0, implicit [[COPY]]
18031776
; CHECK-NEXT: SI_RETURN
18041777
%0:vgpr_32 = COPY $vgpr0
18051778
undef %1.sub0:areg_96_align2 = COPY %0
@@ -1819,12 +1792,11 @@ body: |
18191792
; CHECK-LABEL: name: copy_vgpr32_x4_to_areg128_snop
18201793
; CHECK: liveins: $vgpr0
18211794
; CHECK-NEXT: {{ $}}
1822-
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
1823-
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_128 = COPY [[COPY]]
1824-
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_128 = COPY [[COPY]]
1825-
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub2:areg_128 = COPY [[COPY]]
1826-
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub3:areg_128 = COPY [[COPY]]
1827-
; CHECK-NEXT: S_NOP 0, implicit [[COPY1]]
1795+
; CHECK-NEXT: undef [[COPY:%[0-9]+]].sub0:av_128 = COPY $vgpr0
1796+
; CHECK-NEXT: [[COPY:%[0-9]+]].sub1:av_128 = COPY [[COPY]].sub0
1797+
; CHECK-NEXT: [[COPY:%[0-9]+]].sub2:av_128 = COPY [[COPY]].sub0
1798+
; CHECK-NEXT: [[COPY:%[0-9]+]].sub3:av_128 = COPY [[COPY]].sub0
1799+
; CHECK-NEXT: S_NOP 0, implicit [[COPY]]
18281800
; CHECK-NEXT: SI_RETURN
18291801
%0:vgpr_32 = COPY $vgpr0
18301802
undef %1.sub0:areg_128 = COPY %0
@@ -1846,12 +1818,11 @@ body: |
18461818
; CHECK-LABEL: name: copy_vgpr32_x4_to_areg128_align2_snop
18471819
; CHECK: liveins: $vgpr0
18481820
; CHECK-NEXT: {{ $}}
1849-
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
1850-
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_128_align2 = COPY [[COPY]]
1851-
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_128_align2 = COPY [[COPY]]
1852-
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub2:areg_128_align2 = COPY [[COPY]]
1853-
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub3:areg_128_align2 = COPY [[COPY]]
1854-
; CHECK-NEXT: S_NOP 0, implicit [[COPY1]]
1821+
; CHECK-NEXT: undef [[COPY:%[0-9]+]].sub0:av_128_align2 = COPY $vgpr0
1822+
; CHECK-NEXT: [[COPY:%[0-9]+]].sub1:av_128_align2 = COPY [[COPY]].sub0
1823+
; CHECK-NEXT: [[COPY:%[0-9]+]].sub2:av_128_align2 = COPY [[COPY]].sub0
1824+
; CHECK-NEXT: [[COPY:%[0-9]+]].sub3:av_128_align2 = COPY [[COPY]].sub0
1825+
; CHECK-NEXT: S_NOP 0, implicit [[COPY]]
18551826
; CHECK-NEXT: SI_RETURN
18561827
%0:vgpr_32 = COPY $vgpr0
18571828
undef %1.sub0:areg_128_align2 = COPY %0
@@ -2490,11 +2461,11 @@ body: |
24902461
; CHECK-LABEL: name: copy_vgpr32_vgpr64_to_areg96_coalesce_with_av96
24912462
; CHECK: liveins: $vgpr0, $vgpr1_vgpr2
24922463
; CHECK-NEXT: {{ $}}
2493-
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
2494-
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr1_vgpr2
2495-
; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0:areg_96 = COPY [[COPY]]
2496-
; CHECK-NEXT: [[COPY2:%[0-9]+]].sub1_sub2:areg_96 = COPY [[COPY1]]
2497-
; CHECK-NEXT: S_NOP 0, implicit %2
2464+
; CHECK-NEXT: [[COPY:%[0-9]+]].sub0:vreg_96 = COPY $vgpr0
2465+
; CHECK-NEXT: [[COPY:%[0-9]+]].sub1_sub2:vreg_96 = COPY $vgpr1_vgpr2
2466+
; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0:areg_96 = COPY [[COPY]].sub2
2467+
; CHECK-NEXT: [[COPY2:%[0-9]+]].sub1_sub2:areg_96 = COPY [[COPY]].sub0_sub1
2468+
; CHECK-NEXT: S_NOP 0, implicit [[COPY2]]
24982469
; CHECK-NEXT: SI_RETURN
24992470
undef %0.sub0:vreg_96 = COPY $vgpr0
25002471
%0.sub1_sub2:vreg_96 = COPY $vgpr1_vgpr2

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