Change to builder callback

Author: optimisan

llvm/include/llvm/Passes/CodeGenPassBuilder.h

@@ -506,12 +506,14 @@ template <typename DerivedT, typename TargetMachineT> class CodeGenPassBuilder {
   /// regalloc pass.
   void addRegAllocPass(AddMachinePass &, bool Optimized) const;
   /// Read the --regalloc-npm option to add the next pass in line.
+  /// Returns false if no pass is left in the option.
   bool addRegAllocPassFromOpt(AddMachinePass &,
                               StringRef MatchPassTo = StringRef{}) const;
-  /// Add the next pass in the cli option, or return false if there is no pass
+  /// Add the next pass in the cli option or the pass specified if no pass is
   /// left in the option.
-  template <typename RegAllocPassT>
-  void addRegAllocPassOrOpt(AddMachinePass &, RegAllocPassT Pass) const;
+  template <typename RegAllocPassBuilderT>
+  void addRegAllocPassOrOpt(AddMachinePass &,
+                            RegAllocPassBuilderT PassBuilder) const;
 
   /// Add core register alloator passes which do the actual register assignment
   /// and rewriting. \returns true if any passes were added.
@@ -1111,11 +1113,11 @@ void CodeGenPassBuilder<Derived, TargetMachineT>::addTargetRegisterAllocator(
 }
 
 template <typename Derived, typename TargetMachineT>
-template <typename RegAllocPassT>
+template <typename RegAllocPassBuilderT>
 void CodeGenPassBuilder<Derived, TargetMachineT>::addRegAllocPassOrOpt(
-    AddMachinePass &addPass, RegAllocPassT Pass) const {
+    AddMachinePass &addPass, RegAllocPassBuilderT PassBuilder) const {
   if (!addRegAllocPassFromOpt(addPass))
-    addPass(std::move(Pass));
+    addPass(std::move(PassBuilder()));
 }
 
 template <typename Derived, typename TargetMachineT>

llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

@@ -2212,7 +2212,8 @@ Error AMDGPUCodeGenPassBuilder::addRegAssignmentOptimized(
     AddMachinePass &addPass) const {
   addPass(GCNPreRALongBranchRegPass());
 
-  addRegAllocPassOrOpt(addPass, RAGreedyPass({onlyAllocateSGPRs, "sgpr"}));
+  addRegAllocPassOrOpt(
+      addPass, []() { return RAGreedyPass({onlyAllocateSGPRs, "sgpr"}); });
 
   // Commit allocated register changes. This is mostly necessary because too
   // many things rely on the use lists of the physical registers, such as the
@@ -2232,13 +2233,15 @@ Error AMDGPUCodeGenPassBuilder::addRegAssignmentOptimized(
   addPass(SIPreAllocateWWMRegsPass());
 
   // For allocating other wwm register operands.
-  addRegAllocPassOrOpt(addPass, RAGreedyPass({onlyAllocateWWMRegs, "wwm"}));
+  addRegAllocPassOrOpt(
+      addPass, []() { return RAGreedyPass({onlyAllocateWWMRegs, "wwm"}); });
   addPass(SILowerWWMCopiesPass());
   addPass(VirtRegRewriterPass(false));
   addPass(AMDGPUReserveWWMRegsPass());
 
   // For allocating per-thread VGPRs.
-  addRegAllocPassOrOpt(addPass, RAGreedyPass({onlyAllocateVGPRs, "vgpr"}));
+  addRegAllocPassOrOpt(
+      addPass, []() { return RAGreedyPass({onlyAllocateVGPRs, "vgpr"}); });
 
   // TODO: addPreRewrite();
   addPass(VirtRegRewriterPass(false));

llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp

@@ -39,8 +39,9 @@ class X86CodeGenPassBuilder
 Error X86CodeGenPassBuilder::addRegAssignmentOptimized(
     AddMachinePass &addPass) const {
   if (EnableTileRAPass) {
-    addRegAllocPassOrOpt(addPass,
-                         RAGreedyPass({onlyAllocateTileRegisters, "tile-reg"}));
+    addRegAllocPassOrOpt(addPass, []() {
+      return RAGreedyPass({onlyAllocateTileRegisters, "tile-reg"});
+    });
     // TODO: addPass(X86TileConfigPass());
   }
   return Base::addRegAssignmentOptimized(addPass);