Skip to content

Commit 7318654

Browse files
topperctopperc
authored
[LegalizeTypes][RISCV] Call setTypeListBeforeSoften from ExpandIntRes_FP_TO_XINT if the FP type needs to be softened (#118269)
This avoids an unnecessary sext.w before the libcall.
1 parent d898ff6 commit 7318654

File tree

5 files changed

+65
-134
lines changed

5 files changed

+65
-134
lines changed

‎llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp‎

Lines changed: 10 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3995,11 +3995,18 @@ void DAGTypeLegalizer::ExpandIntRes_FP_TO_XINT(SDNode *N, SDValue &Lo,
39953995
Op = fpExtendHelper(Op, Chain, IsStrict, MVT::f32, dl, DAG);
39963996
}
39973997

3998-
RTLIB::Libcall LC = IsSigned ? RTLIB::getFPTOSINT(Op.getValueType(), VT)
3999-
: RTLIB::getFPTOUINT(Op.getValueType(), VT);
3998+
// NOTE: We need a variable that lives across makeLibCall so
3999+
// CallOptions.setTypeListBeforeSoften can save a reference to it.
4000+
EVT OpVT = Op.getValueType();
4001+
4002+
RTLIB::Libcall LC =
4003+
IsSigned ? RTLIB::getFPTOSINT(OpVT, VT) : RTLIB::getFPTOUINT(OpVT, VT);
40004004
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-xint conversion!");
40014005
TargetLowering::MakeLibCallOptions CallOptions;
4002-
CallOptions.setSExt(true);
4006+
if (getTypeAction(Op.getValueType()) == TargetLowering::TypeSoftenFloat)
4007+
CallOptions.setTypeListBeforeSoften(OpVT, VT);
4008+
else
4009+
CallOptions.setSExt(true);
40034010
std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, VT, Op,
40044011
CallOptions, dl, Chain);
40054012
SplitInteger(Tmp.first, Lo, Hi);

‎llvm/test/CodeGen/RISCV/rv64-float-convert-strict.ll‎

Lines changed: 20 additions & 54 deletions
Original file line numberDiff line numberDiff line change
@@ -7,65 +7,27 @@
77
; RUN: -disable-strictnode-mutation | FileCheck %s -check-prefixes=CHECK,RV64IFINX
88

99
define i128 @fptosi_f32_to_i128(float %a) nounwind strictfp {
10-
; RV64I-LABEL: fptosi_f32_to_i128:
11-
; RV64I: # %bb.0:
12-
; RV64I-NEXT: addi sp, sp, -16
13-
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
14-
; RV64I-NEXT: sext.w a0, a0
15-
; RV64I-NEXT: call __fixsfti
16-
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
17-
; RV64I-NEXT: addi sp, sp, 16
18-
; RV64I-NEXT: ret
19-
;
20-
; RV64IF-LABEL: fptosi_f32_to_i128:
21-
; RV64IF: # %bb.0:
22-
; RV64IF-NEXT: addi sp, sp, -16
23-
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
24-
; RV64IF-NEXT: call __fixsfti
25-
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
26-
; RV64IF-NEXT: addi sp, sp, 16
27-
; RV64IF-NEXT: ret
28-
;
29-
; RV64IFINX-LABEL: fptosi_f32_to_i128:
30-
; RV64IFINX: # %bb.0:
31-
; RV64IFINX-NEXT: addi sp, sp, -16
32-
; RV64IFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
33-
; RV64IFINX-NEXT: call __fixsfti
34-
; RV64IFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
35-
; RV64IFINX-NEXT: addi sp, sp, 16
36-
; RV64IFINX-NEXT: ret
10+
; CHECK-LABEL: fptosi_f32_to_i128:
11+
; CHECK: # %bb.0:
12+
; CHECK-NEXT: addi sp, sp, -16
13+
; CHECK-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
14+
; CHECK-NEXT: call __fixsfti
15+
; CHECK-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
16+
; CHECK-NEXT: addi sp, sp, 16
17+
; CHECK-NEXT: ret
3718
%1 = call i128 @llvm.experimental.constrained.fptosi.i128.f32(float %a, metadata !"fpexcept.strict")
3819
ret i128 %1
3920
}
4021

4122
define i128 @fptoui_f32_to_i128(float %a) nounwind strictfp {
42-
; RV64I-LABEL: fptoui_f32_to_i128:
43-
; RV64I: # %bb.0:
44-
; RV64I-NEXT: addi sp, sp, -16
45-
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
46-
; RV64I-NEXT: sext.w a0, a0
47-
; RV64I-NEXT: call __fixunssfti
48-
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
49-
; RV64I-NEXT: addi sp, sp, 16
50-
; RV64I-NEXT: ret
51-
;
52-
; RV64IF-LABEL: fptoui_f32_to_i128:
53-
; RV64IF: # %bb.0:
54-
; RV64IF-NEXT: addi sp, sp, -16
55-
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
56-
; RV64IF-NEXT: call __fixunssfti
57-
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
58-
; RV64IF-NEXT: addi sp, sp, 16
59-
; RV64IF-NEXT: ret
60-
;
61-
; RV64IFINX-LABEL: fptoui_f32_to_i128:
62-
; RV64IFINX: # %bb.0:
63-
; RV64IFINX-NEXT: addi sp, sp, -16
64-
; RV64IFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
65-
; RV64IFINX-NEXT: call __fixunssfti
66-
; RV64IFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
67-
; RV64IFINX-NEXT: addi sp, sp, 16
68-
; RV64IFINX-NEXT: ret
23+
; CHECK-LABEL: fptoui_f32_to_i128:
24+
; CHECK: # %bb.0:
25+
; CHECK-NEXT: addi sp, sp, -16
26+
; CHECK-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
27+
; CHECK-NEXT: call __fixunssfti
28+
; CHECK-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
29+
; CHECK-NEXT: addi sp, sp, 16
30+
; CHECK-NEXT: ret
6931
%1 = call i128 @llvm.experimental.constrained.fptoui.i128.f32(float %a, metadata !"fpexcept.strict")
7032
ret i128 %1
7133
}
@@ -95,3 +57,7 @@ define float @uitofp_i128_to_f32(i128 %a) nounwind strictfp {
9557
%1 = call float @llvm.experimental.constrained.uitofp.f32.i128(i128 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")
9658
ret float %1
9759
}
60+
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
61+
; RV64I: {{.*}}
62+
; RV64IF: {{.*}}
63+
; RV64IFINX: {{.*}}

‎llvm/test/CodeGen/RISCV/rv64-float-convert.ll‎

Lines changed: 27 additions & 65 deletions
Original file line numberDiff line numberDiff line change
@@ -7,65 +7,27 @@
77
; RUN: | FileCheck %s -check-prefixes=CHECK,RV64IZFINX
88

99
define i128 @fptosi_f32_to_i128(float %a) nounwind {
10-
; RV64I-LABEL: fptosi_f32_to_i128:
11-
; RV64I: # %bb.0:
12-
; RV64I-NEXT: addi sp, sp, -16
13-
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
14-
; RV64I-NEXT: sext.w a0, a0
15-
; RV64I-NEXT: call __fixsfti
16-
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
17-
; RV64I-NEXT: addi sp, sp, 16
18-
; RV64I-NEXT: ret
19-
;
20-
; RV64IF-LABEL: fptosi_f32_to_i128:
21-
; RV64IF: # %bb.0:
22-
; RV64IF-NEXT: addi sp, sp, -16
23-
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
24-
; RV64IF-NEXT: call __fixsfti
25-
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
26-
; RV64IF-NEXT: addi sp, sp, 16
27-
; RV64IF-NEXT: ret
28-
;
29-
; RV64IZFINX-LABEL: fptosi_f32_to_i128:
30-
; RV64IZFINX: # %bb.0:
31-
; RV64IZFINX-NEXT: addi sp, sp, -16
32-
; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
33-
; RV64IZFINX-NEXT: call __fixsfti
34-
; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
35-
; RV64IZFINX-NEXT: addi sp, sp, 16
36-
; RV64IZFINX-NEXT: ret
10+
; CHECK-LABEL: fptosi_f32_to_i128:
11+
; CHECK: # %bb.0:
12+
; CHECK-NEXT: addi sp, sp, -16
13+
; CHECK-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
14+
; CHECK-NEXT: call __fixsfti
15+
; CHECK-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
16+
; CHECK-NEXT: addi sp, sp, 16
17+
; CHECK-NEXT: ret
3718
%1 = fptosi float %a to i128
3819
ret i128 %1
3920
}
4021

4122
define i128 @fptoui_f32_to_i128(float %a) nounwind {
42-
; RV64I-LABEL: fptoui_f32_to_i128:
43-
; RV64I: # %bb.0:
44-
; RV64I-NEXT: addi sp, sp, -16
45-
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
46-
; RV64I-NEXT: sext.w a0, a0
47-
; RV64I-NEXT: call __fixunssfti
48-
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
49-
; RV64I-NEXT: addi sp, sp, 16
50-
; RV64I-NEXT: ret
51-
;
52-
; RV64IF-LABEL: fptoui_f32_to_i128:
53-
; RV64IF: # %bb.0:
54-
; RV64IF-NEXT: addi sp, sp, -16
55-
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
56-
; RV64IF-NEXT: call __fixunssfti
57-
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
58-
; RV64IF-NEXT: addi sp, sp, 16
59-
; RV64IF-NEXT: ret
60-
;
61-
; RV64IZFINX-LABEL: fptoui_f32_to_i128:
62-
; RV64IZFINX: # %bb.0:
63-
; RV64IZFINX-NEXT: addi sp, sp, -16
64-
; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
65-
; RV64IZFINX-NEXT: call __fixunssfti
66-
; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
67-
; RV64IZFINX-NEXT: addi sp, sp, 16
68-
; RV64IZFINX-NEXT: ret
23+
; CHECK-LABEL: fptoui_f32_to_i128:
24+
; CHECK: # %bb.0:
25+
; CHECK-NEXT: addi sp, sp, -16
26+
; CHECK-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
27+
; CHECK-NEXT: call __fixunssfti
28+
; CHECK-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
29+
; CHECK-NEXT: addi sp, sp, 16
30+
; CHECK-NEXT: ret
6931
%1 = fptoui float %a to i128
7032
ret i128 %1
7133
}
@@ -107,38 +69,38 @@ define i128 @fptosi_sat_f32_to_i128(float %a) nounwind {
10769
; RV64I-NEXT: sd s3, 24(sp) # 8-byte Folded Spill
10870
; RV64I-NEXT: sd s4, 16(sp) # 8-byte Folded Spill
10971
; RV64I-NEXT: sd s5, 8(sp) # 8-byte Folded Spill
110-
; RV64I-NEXT: mv s0, a0
72+
; RV64I-NEXT: mv s1, a0
11173
; RV64I-NEXT: lui a1, 1044480
11274
; RV64I-NEXT: call __gesf2
113-
; RV64I-NEXT: mv s1, a0
114-
; RV64I-NEXT: sext.w a0, s0
115-
; RV64I-NEXT: call __fixsfti
11675
; RV64I-NEXT: mv s2, a0
76+
; RV64I-NEXT: mv a0, s1
77+
; RV64I-NEXT: call __fixsfti
78+
; RV64I-NEXT: mv s0, a0
11779
; RV64I-NEXT: mv s3, a1
11880
; RV64I-NEXT: li s5, -1
119-
; RV64I-NEXT: bgez s1, .LBB4_2
81+
; RV64I-NEXT: bgez s2, .LBB4_2
12082
; RV64I-NEXT: # %bb.1:
12183
; RV64I-NEXT: slli s3, s5, 63
12284
; RV64I-NEXT: .LBB4_2:
12385
; RV64I-NEXT: lui a1, 520192
12486
; RV64I-NEXT: addiw a1, a1, -1
125-
; RV64I-NEXT: mv a0, s0
87+
; RV64I-NEXT: mv a0, s1
12688
; RV64I-NEXT: call __gtsf2
12789
; RV64I-NEXT: mv s4, a0
12890
; RV64I-NEXT: blez a0, .LBB4_4
12991
; RV64I-NEXT: # %bb.3:
13092
; RV64I-NEXT: srli s3, s5, 1
13193
; RV64I-NEXT: .LBB4_4:
132-
; RV64I-NEXT: mv a0, s0
133-
; RV64I-NEXT: mv a1, s0
94+
; RV64I-NEXT: mv a0, s1
95+
; RV64I-NEXT: mv a1, s1
13496
; RV64I-NEXT: call __unordsf2
13597
; RV64I-NEXT: snez a0, a0
136-
; RV64I-NEXT: slti a1, s1, 0
98+
; RV64I-NEXT: slti a1, s2, 0
13799
; RV64I-NEXT: sgtz a2, s4
138100
; RV64I-NEXT: addi a0, a0, -1
139101
; RV64I-NEXT: addi a3, a1, -1
140102
; RV64I-NEXT: and a1, a0, s3
141-
; RV64I-NEXT: and a3, a3, s2
103+
; RV64I-NEXT: and a3, a3, s0
142104
; RV64I-NEXT: neg a2, a2
143105
; RV64I-NEXT: or a2, a2, a3
144106
; RV64I-NEXT: and a0, a0, a2
@@ -249,7 +211,7 @@ define i128 @fptoui_sat_f32_to_i128(float %a) nounwind {
249211
; RV64I-NEXT: call __gesf2
250212
; RV64I-NEXT: slti a0, a0, 0
251213
; RV64I-NEXT: addi s2, a0, -1
252-
; RV64I-NEXT: sext.w a0, s0
214+
; RV64I-NEXT: mv a0, s0
253215
; RV64I-NEXT: call __fixunssfti
254216
; RV64I-NEXT: and a0, s2, a0
255217
; RV64I-NEXT: and a1, s2, a1

‎llvm/test/CodeGen/RISCV/rv64-half-convert-strict.ll‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,6 @@ define i128 @fptosi_f16_to_i128(half %a) nounwind strictfp {
1515
; RV64I-NEXT: addi sp, sp, -16
1616
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1717
; RV64I-NEXT: call __extendhfsf2
18-
; RV64I-NEXT: sext.w a0, a0
1918
; RV64I-NEXT: call __fixsfti
2019
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
2120
; RV64I-NEXT: addi sp, sp, 16
@@ -48,7 +47,6 @@ define i128 @fptoui_f16_to_i128(half %a) nounwind strictfp {
4847
; RV64I-NEXT: addi sp, sp, -16
4948
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
5049
; RV64I-NEXT: call __extendhfsf2
51-
; RV64I-NEXT: sext.w a0, a0
5250
; RV64I-NEXT: call __fixunssfti
5351
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
5452
; RV64I-NEXT: addi sp, sp, 16

‎llvm/test/CodeGen/RISCV/rv64-half-convert.ll‎

Lines changed: 8 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -76,7 +76,6 @@ define i128 @fptosi_f16_to_i128(half %a) nounwind {
7676
; RV64I-NEXT: addi sp, sp, -16
7777
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
7878
; RV64I-NEXT: call __extendhfsf2
79-
; RV64I-NEXT: sext.w a0, a0
8079
; RV64I-NEXT: call __fixsfti
8180
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
8281
; RV64I-NEXT: addi sp, sp, 16
@@ -109,7 +108,6 @@ define i128 @fptoui_f16_to_i128(half %a) nounwind {
109108
; RV64I-NEXT: addi sp, sp, -16
110109
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
111110
; RV64I-NEXT: call __extendhfsf2
112-
; RV64I-NEXT: sext.w a0, a0
113111
; RV64I-NEXT: call __fixunssfti
114112
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
115113
; RV64I-NEXT: addi sp, sp, 16
@@ -148,13 +146,13 @@ define i128 @fptosi_sat_f16_to_i128(half %a) nounwind {
148146
; RV64I-NEXT: sd s4, 16(sp) # 8-byte Folded Spill
149147
; RV64I-NEXT: sd s5, 8(sp) # 8-byte Folded Spill
150148
; RV64I-NEXT: call __extendhfsf2
151-
; RV64I-NEXT: mv s1, a0
149+
; RV64I-NEXT: mv s2, a0
152150
; RV64I-NEXT: lui a1, 1044480
153151
; RV64I-NEXT: call __gesf2
154152
; RV64I-NEXT: mv s0, a0
155-
; RV64I-NEXT: sext.w a0, s1
153+
; RV64I-NEXT: mv a0, s2
156154
; RV64I-NEXT: call __fixsfti
157-
; RV64I-NEXT: mv s2, a0
155+
; RV64I-NEXT: mv s1, a0
158156
; RV64I-NEXT: mv s3, a1
159157
; RV64I-NEXT: li s5, -1
160158
; RV64I-NEXT: bgez s0, .LBB4_2
@@ -163,15 +161,15 @@ define i128 @fptosi_sat_f16_to_i128(half %a) nounwind {
163161
; RV64I-NEXT: .LBB4_2:
164162
; RV64I-NEXT: lui a1, 520192
165163
; RV64I-NEXT: addiw a1, a1, -1
166-
; RV64I-NEXT: mv a0, s1
164+
; RV64I-NEXT: mv a0, s2
167165
; RV64I-NEXT: call __gtsf2
168166
; RV64I-NEXT: mv s4, a0
169167
; RV64I-NEXT: blez a0, .LBB4_4
170168
; RV64I-NEXT: # %bb.3:
171169
; RV64I-NEXT: srli s3, s5, 1
172170
; RV64I-NEXT: .LBB4_4:
173-
; RV64I-NEXT: mv a0, s1
174-
; RV64I-NEXT: mv a1, s1
171+
; RV64I-NEXT: mv a0, s2
172+
; RV64I-NEXT: mv a1, s2
175173
; RV64I-NEXT: call __unordsf2
176174
; RV64I-NEXT: snez a0, a0
177175
; RV64I-NEXT: sgtz a1, s4
@@ -180,7 +178,7 @@ define i128 @fptosi_sat_f16_to_i128(half %a) nounwind {
180178
; RV64I-NEXT: neg a3, a1
181179
; RV64I-NEXT: addi a2, a2, -1
182180
; RV64I-NEXT: and a1, a0, s3
183-
; RV64I-NEXT: and a2, a2, s2
181+
; RV64I-NEXT: and a2, a2, s1
184182
; RV64I-NEXT: or a2, a3, a2
185183
; RV64I-NEXT: and a0, a0, a2
186184
; RV64I-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
@@ -292,7 +290,7 @@ define i128 @fptoui_sat_f16_to_i128(half %a) nounwind {
292290
; RV64I-NEXT: call __gesf2
293291
; RV64I-NEXT: slti a0, a0, 0
294292
; RV64I-NEXT: addi s2, a0, -1
295-
; RV64I-NEXT: sext.w a0, s0
293+
; RV64I-NEXT: mv a0, s0
296294
; RV64I-NEXT: call __fixunssfti
297295
; RV64I-NEXT: and a0, s2, a0
298296
; RV64I-NEXT: and a1, s2, a1

0 commit comments

Comments
 (0)