@@ -229,9 +229,6 @@ class SPIRVInstructionSelector : public InstructionSelector {
229229 bool selectSpvThreadId (Register ResVReg, const SPIRVType *ResType,
230230 MachineInstr &I) const ;
231231
232- bool selectRadians (Register ResVReg, const SPIRVType *ResType,
233- MachineInstr &I) const ;
234-
235232 bool selectUnmergeValues (MachineInstr &I) const ;
236233
237234 // Utilities
@@ -1754,45 +1751,6 @@ bool SPIRVInstructionSelector::selectSign(Register ResVReg,
17541751 return Result;
17551752}
17561753
1757- <<<<<<< HEAD
1758- =======
1759- bool SPIRVInstructionSelector::selectStep (Register ResVReg,
1760- const SPIRVType *ResType,
1761- MachineInstr &I) const {
1762-
1763- assert (I.getNumOperands () == 4 );
1764- assert (I.getOperand (2 ).isReg ());
1765- assert (I.getOperand (3 ).isReg ());
1766- MachineBasicBlock &BB = *I.getParent ();
1767-
1768- return BuildMI (BB, I, I.getDebugLoc (), TII.get (SPIRV::OpExtInst))
1769- .addDef (ResVReg)
1770- .addUse (GR.getSPIRVTypeID (ResType))
1771- .addImm (static_cast <uint32_t >(SPIRV::InstructionSet::GLSL_std_450))
1772- .addImm (GL::Step)
1773- .addUse (I.getOperand (2 ).getReg ())
1774- .addUse (I.getOperand (3 ).getReg ())
1775- .constrainAllUses (TII, TRI, RBI);
1776- }
1777-
1778- bool SPIRVInstructionSelector::selectRadians (Register ResVReg,
1779- const SPIRVType *ResType,
1780- MachineInstr &I) const {
1781-
1782- assert (I.getNumOperands () == 3 );
1783- assert (I.getOperand (2 ).isReg ());
1784- MachineBasicBlock &BB = *I.getParent ();
1785-
1786- return BuildMI (BB, I, I.getDebugLoc (), TII.get (SPIRV::OpExtInst))
1787- .addDef (ResVReg)
1788- .addUse (GR.getSPIRVTypeID (ResType))
1789- .addImm (static_cast <uint32_t >(SPIRV::InstructionSet::GLSL_std_450))
1790- .addImm (GL::Radians)
1791- .addUse (I.getOperand (2 ).getReg ())
1792- .constrainAllUses (TII, TRI, RBI);
1793- }
1794-
1795- >>>>>>> c520937ac3f9 (Added radians selection for spirv)
17961754bool SPIRVInstructionSelector::selectBitreverse (Register ResVReg,
17971755 const SPIRVType *ResType,
17981756 MachineInstr &I) const {
@@ -2575,8 +2533,9 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
25752533 .addUse (GR.getOrCreateConstInt (3 , I, IntTy, TII));
25762534 }
25772535 case Intrinsic::spv_step:
2578- <<<<<<< HEAD
25792536 return selectExtInst (ResVReg, ResType, I, CL::step, GL::Step);
2537+ case Intrinsic::spv_radians:
2538+ return selectExtInst (ResVReg, ResType, I, CL::radians, GL::Radians);
25802539 // Discard intrinsics which we do not expect to actually represent code after
25812540 // lowering or intrinsics which are not implemented but should not crash when
25822541 // found in a customer's LLVM IR input.
@@ -2585,11 +2544,6 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
25852544 case Intrinsic::instrprof_value_profile:
25862545 break ;
25872546 // Discard internal intrinsics.
2588- =======
2589- return selectStep (ResVReg, ResType, I);
2590- case Intrinsic::spv_radians:
2591- return selectRadians (ResVReg, ResType, I);
2592- >>>>>>> c520937ac3f9 (Added radians selection for spirv)
25932547 case Intrinsic::spv_value_md:
25942548 break ;
25952549 default : {
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