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AMDGPU: Add codegen for atomicrmw operations usub_cond and usub_sat (#141068)
Split off from #105553 as per discussion there.
1 parent db84960 commit 740a3ad

36 files changed

+10340
-445
lines changed

‎llvm/include/llvm/IR/IntrinsicsAMDGPU.td‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1703,6 +1703,7 @@ def int_amdgcn_raw_buffer_atomic_xor : AMDGPURawBufferAtomic;
17031703
def int_amdgcn_raw_buffer_atomic_inc : AMDGPURawBufferAtomic;
17041704
def int_amdgcn_raw_buffer_atomic_dec : AMDGPURawBufferAtomic;
17051705
def int_amdgcn_raw_buffer_atomic_cond_sub_u32 : AMDGPURawBufferAtomic;
1706+
def int_amdgcn_raw_buffer_atomic_sub_clamp_u32 : AMDGPURawBufferAtomic;
17061707
def int_amdgcn_raw_buffer_atomic_cmpswap : Intrinsic<
17071708
[llvm_anyint_ty],
17081709
[LLVMMatchType<0>, // src(VGPR)
@@ -1740,6 +1741,7 @@ def int_amdgcn_raw_ptr_buffer_atomic_xor : AMDGPURawPtrBufferAtomic;
17401741
def int_amdgcn_raw_ptr_buffer_atomic_inc : AMDGPURawPtrBufferAtomic;
17411742
def int_amdgcn_raw_ptr_buffer_atomic_dec : AMDGPURawPtrBufferAtomic;
17421743
def int_amdgcn_raw_ptr_buffer_atomic_cond_sub_u32 : AMDGPURawPtrBufferAtomic;
1744+
def int_amdgcn_raw_ptr_buffer_atomic_sub_clamp_u32 : AMDGPURawPtrBufferAtomic;
17431745
def int_amdgcn_raw_ptr_buffer_atomic_cmpswap : Intrinsic<
17441746
[llvm_anyint_ty],
17451747
[LLVMMatchType<0>, // src(VGPR)
@@ -1781,6 +1783,7 @@ def int_amdgcn_struct_buffer_atomic_xor : AMDGPUStructBufferAtomic;
17811783
def int_amdgcn_struct_buffer_atomic_inc : AMDGPUStructBufferAtomic;
17821784
def int_amdgcn_struct_buffer_atomic_dec : AMDGPUStructBufferAtomic;
17831785
def int_amdgcn_struct_buffer_atomic_cond_sub_u32 : AMDGPUStructBufferAtomic;
1786+
def int_amdgcn_struct_buffer_atomic_sub_clamp_u32 : AMDGPUStructBufferAtomic;
17841787
def int_amdgcn_struct_buffer_atomic_cmpswap : Intrinsic<
17851788
[llvm_anyint_ty],
17861789
[LLVMMatchType<0>, // src(VGPR)
@@ -1817,6 +1820,7 @@ def int_amdgcn_struct_ptr_buffer_atomic_xor : AMDGPUStructPtrBufferAtomic;
18171820
def int_amdgcn_struct_ptr_buffer_atomic_inc : AMDGPUStructPtrBufferAtomic;
18181821
def int_amdgcn_struct_ptr_buffer_atomic_dec : AMDGPUStructPtrBufferAtomic;
18191822
def int_amdgcn_struct_ptr_buffer_atomic_cond_sub_u32 : AMDGPUStructPtrBufferAtomic;
1823+
def int_amdgcn_struct_ptr_buffer_atomic_sub_clamp_u32 : AMDGPUStructPtrBufferAtomic;
18201824
def int_amdgcn_struct_ptr_buffer_atomic_cmpswap : Intrinsic<
18211825
[llvm_anyint_ty],
18221826
[LLVMMatchType<0>, // src(VGPR)

‎llvm/lib/Target/AMDGPU/AMDGPU.td‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2596,6 +2596,10 @@ def HasAtomicFMinFMaxF64FlatInsts :
25962596
Predicate<"Subtarget->hasAtomicFMinFMaxF64FlatInsts()">,
25972597
AssemblerPredicate<(any_of FeatureAtomicFMinFMaxF64FlatInsts)>;
25982598

2599+
def HasAtomicCondSubClampFlatInsts :
2600+
Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX12">,
2601+
AssemblerPredicate<(all_of FeatureGFX12Insts)>;
2602+
25992603
def HasLdsAtomicAddF64 :
26002604
Predicate<"Subtarget->hasLdsAtomicAddF64()">,
26012605
AssemblerPredicate<(any_of FeatureGFX90AInsts, FeatureGFX1250Insts)>;
@@ -2926,6 +2930,10 @@ def HasFmaLegacy32 : Predicate<"Subtarget->hasGFX10_3Insts()">,
29262930
def HasAtomicDsPkAdd16Insts : Predicate<"Subtarget->hasAtomicDsPkAdd16Insts()">,
29272931
AssemblerPredicate<(any_of FeatureAtomicDsPkAdd16Insts)>;
29282932

2933+
def HasAtomicDsCondSubClampInsts :
2934+
Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX12">,
2935+
AssemblerPredicate<(all_of FeatureGFX12Insts)>;
2936+
29292937
def HasAtomicFlatPkAdd16Insts : Predicate<"Subtarget->hasAtomicFlatPkAdd16Insts()">,
29302938
AssemblerPredicate<(any_of FeatureAtomicFlatPkAdd16Insts)>;
29312939

‎llvm/lib/Target/AMDGPU/AMDGPUGISel.td‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -288,6 +288,8 @@ def : GINodeEquiv<G_AMDGPU_TBUFFER_STORE_FORMAT_D16, SItbuffer_store_d16>;
288288
// FIXME: Check MMO is atomic
289289
def : GINodeEquiv<G_ATOMICRMW_UINC_WRAP, atomic_load_uinc_wrap_glue>;
290290
def : GINodeEquiv<G_ATOMICRMW_UDEC_WRAP, atomic_load_udec_wrap_glue>;
291+
def : GINodeEquiv<G_ATOMICRMW_USUB_COND, atomic_load_usub_cond_glue>;
292+
def : GINodeEquiv<G_ATOMICRMW_USUB_SAT, atomic_load_usub_sat_glue>;
291293
def : GINodeEquiv<G_ATOMICRMW_FMIN, atomic_load_fmin_glue>;
292294
def : GINodeEquiv<G_ATOMICRMW_FMAX, atomic_load_fmax_glue>;
293295

@@ -308,6 +310,7 @@ def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_FMIN, SIbuffer_atomic_fmin>;
308310
def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_FMAX, SIbuffer_atomic_fmax>;
309311
def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_CMPSWAP, SIbuffer_atomic_cmpswap>;
310312
def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_COND_SUB_U32, SIbuffer_atomic_cond_sub_u32>;
313+
def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_SUB_CLAMP_U32, SIbuffer_atomic_csub>;
311314
def : GINodeEquiv<G_AMDGPU_S_BUFFER_LOAD, SIsbuffer_load>;
312315
def : GINodeEquiv<G_AMDGPU_S_BUFFER_LOAD_SBYTE, SIsbuffer_load_byte>;
313316
def : GINodeEquiv<G_AMDGPU_S_BUFFER_LOAD_UBYTE, SIsbuffer_load_ubyte>;

‎llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4201,6 +4201,8 @@ bool AMDGPUInstructionSelector::select(MachineInstr &I) {
42014201
case TargetOpcode::G_ATOMICRMW_UMAX:
42024202
case TargetOpcode::G_ATOMICRMW_UINC_WRAP:
42034203
case TargetOpcode::G_ATOMICRMW_UDEC_WRAP:
4204+
case TargetOpcode::G_ATOMICRMW_USUB_COND:
4205+
case TargetOpcode::G_ATOMICRMW_USUB_SAT:
42044206
case TargetOpcode::G_ATOMICRMW_FADD:
42054207
case TargetOpcode::G_ATOMICRMW_FMIN:
42064208
case TargetOpcode::G_ATOMICRMW_FMAX:

‎llvm/lib/Target/AMDGPU/AMDGPUInstructions.td‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -695,6 +695,8 @@ defm atomic_load_fmin : binary_atomic_op_fp_all_as<atomic_load_fmin>;
695695
defm atomic_load_fmax : binary_atomic_op_fp_all_as<atomic_load_fmax>;
696696
defm atomic_load_uinc_wrap : binary_atomic_op_all_as<atomic_load_uinc_wrap>;
697697
defm atomic_load_udec_wrap : binary_atomic_op_all_as<atomic_load_udec_wrap>;
698+
defm atomic_load_usub_cond : binary_atomic_op_all_as<atomic_load_usub_cond>;
699+
defm atomic_load_usub_sat : binary_atomic_op_all_as<atomic_load_usub_sat>;
698700
defm AMDGPUatomic_cmp_swap : binary_atomic_op_all_as<AMDGPUatomic_cmp_swap>;
699701

700702
def load_align8_local : PatFrag<(ops node:$ptr), (load_local node:$ptr)>,

‎llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp‎

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1722,6 +1722,13 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
17221722
Atomics.legalFor({{S32, FlatPtr}, {S64, FlatPtr}});
17231723
}
17241724

1725+
auto &Atomics32 =
1726+
getActionDefinitionsBuilder({G_ATOMICRMW_USUB_COND, G_ATOMICRMW_USUB_SAT})
1727+
.legalFor({{S32, GlobalPtr}, {S32, LocalPtr}, {S32, RegionPtr}});
1728+
if (ST.hasFlatAddressSpace()) {
1729+
Atomics32.legalFor({{S32, FlatPtr}});
1730+
}
1731+
17251732
// TODO: v2bf16 operations, and fat buffer pointer support.
17261733
auto &Atomic = getActionDefinitionsBuilder(G_ATOMICRMW_FADD);
17271734
if (ST.hasLDSFPAtomicAddF32()) {
@@ -6561,8 +6568,15 @@ static unsigned getBufferAtomicPseudo(Intrinsic::ID IntrID) {
65616568
case Intrinsic::amdgcn_struct_buffer_atomic_fmax:
65626569
case Intrinsic::amdgcn_struct_ptr_buffer_atomic_fmax:
65636570
return AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FMAX;
6571+
case Intrinsic::amdgcn_raw_buffer_atomic_sub_clamp_u32:
6572+
case Intrinsic::amdgcn_raw_ptr_buffer_atomic_sub_clamp_u32:
6573+
case Intrinsic::amdgcn_struct_buffer_atomic_sub_clamp_u32:
6574+
case Intrinsic::amdgcn_struct_ptr_buffer_atomic_sub_clamp_u32:
6575+
return AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SUB_CLAMP_U32;
65646576
case Intrinsic::amdgcn_raw_buffer_atomic_cond_sub_u32:
6577+
case Intrinsic::amdgcn_raw_ptr_buffer_atomic_cond_sub_u32:
65656578
case Intrinsic::amdgcn_struct_buffer_atomic_cond_sub_u32:
6579+
case Intrinsic::amdgcn_struct_ptr_buffer_atomic_cond_sub_u32:
65666580
return AMDGPU::G_AMDGPU_BUFFER_ATOMIC_COND_SUB_U32;
65676581
default:
65686582
llvm_unreachable("unhandled atomic opcode");
@@ -7970,6 +7984,14 @@ bool AMDGPULegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
79707984
case Intrinsic::amdgcn_raw_ptr_buffer_atomic_fmax:
79717985
case Intrinsic::amdgcn_struct_buffer_atomic_fmax:
79727986
case Intrinsic::amdgcn_struct_ptr_buffer_atomic_fmax:
7987+
case Intrinsic::amdgcn_raw_buffer_atomic_sub_clamp_u32:
7988+
case Intrinsic::amdgcn_raw_ptr_buffer_atomic_sub_clamp_u32:
7989+
case Intrinsic::amdgcn_struct_buffer_atomic_sub_clamp_u32:
7990+
case Intrinsic::amdgcn_struct_ptr_buffer_atomic_sub_clamp_u32:
7991+
case Intrinsic::amdgcn_raw_buffer_atomic_cond_sub_u32:
7992+
case Intrinsic::amdgcn_raw_ptr_buffer_atomic_cond_sub_u32:
7993+
case Intrinsic::amdgcn_struct_buffer_atomic_cond_sub_u32:
7994+
case Intrinsic::amdgcn_struct_ptr_buffer_atomic_cond_sub_u32:
79737995
case Intrinsic::amdgcn_raw_buffer_atomic_fadd:
79747996
case Intrinsic::amdgcn_raw_ptr_buffer_atomic_fadd:
79757997
case Intrinsic::amdgcn_struct_buffer_atomic_fadd:

‎llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp‎

Lines changed: 9 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1748,6 +1748,12 @@ Value *SplitPtrStructs::handleMemoryInst(Instruction *I, Value *Arg, Value *Ptr,
17481748
case AtomicRMWInst::FMin:
17491749
IID = Intrinsic::amdgcn_raw_ptr_buffer_atomic_fmin;
17501750
break;
1751+
case AtomicRMWInst::USubCond:
1752+
IID = Intrinsic::amdgcn_raw_ptr_buffer_atomic_cond_sub_u32;
1753+
break;
1754+
case AtomicRMWInst::USubSat:
1755+
IID = Intrinsic::amdgcn_raw_ptr_buffer_atomic_sub_clamp_u32;
1756+
break;
17511757
case AtomicRMWInst::FSub: {
17521758
reportFatalUsageError(
17531759
"atomic floating point subtraction not supported for "
@@ -1773,14 +1779,12 @@ Value *SplitPtrStructs::handleMemoryInst(Instruction *I, Value *Arg, Value *Ptr,
17731779
break;
17741780
case AtomicRMWInst::UIncWrap:
17751781
case AtomicRMWInst::UDecWrap:
1776-
reportFatalUsageError("wrapping increment/decrement not supported for "
1777-
"buffer resources and should've ben expanded away");
1782+
reportFatalUsageError(
1783+
"wrapping increment/decrement not supported for "
1784+
"buffer resources and should've been expanded away");
17781785
break;
17791786
case AtomicRMWInst::BAD_BINOP:
17801787
llvm_unreachable("Not sure how we got a bad binop");
1781-
case AtomicRMWInst::USubCond:
1782-
case AtomicRMWInst::USubSat:
1783-
break;
17841788
}
17851789
}
17861790

‎llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3111,6 +3111,8 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
31113111
case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_XOR:
31123112
case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_INC:
31133113
case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_DEC:
3114+
case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SUB_CLAMP_U32:
3115+
case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_COND_SUB_U32:
31143116
case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FADD:
31153117
case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FMIN:
31163118
case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FMAX: {
@@ -4499,6 +4501,8 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
44994501
case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_XOR:
45004502
case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_INC:
45014503
case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_DEC:
4504+
case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SUB_CLAMP_U32:
4505+
case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_COND_SUB_U32:
45024506
case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FADD:
45034507
case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FMIN:
45044508
case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FMAX: {
@@ -5705,6 +5709,8 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
57055709
case AMDGPU::G_ATOMICRMW_FMAX:
57065710
case AMDGPU::G_ATOMICRMW_UINC_WRAP:
57075711
case AMDGPU::G_ATOMICRMW_UDEC_WRAP:
5712+
case AMDGPU::G_ATOMICRMW_USUB_COND:
5713+
case AMDGPU::G_ATOMICRMW_USUB_SAT:
57085714
case AMDGPU::G_AMDGPU_ATOMIC_CMPXCHG: {
57095715
OpdsMapping[0] = getVGPROpMapping(MI.getOperand(0).getReg(), MRI, *TRI);
57105716
OpdsMapping[1] = getValueMappingForPtr(MRI, MI.getOperand(1).getReg());

‎llvm/lib/Target/AMDGPU/DSInstructions.td‎

Lines changed: 10 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -890,10 +890,8 @@ multiclass DSAtomicRetNoRetPatIntrinsic_mc<DS_Pseudo inst, DS_Pseudo noRetInst,
890890
ValueType vt, string frag> {
891891
def : DSAtomicRetPat<inst, vt,
892892
!cast<PatFrag>(frag#"_local_addrspace")>;
893-
894-
let OtherPredicates = [HasAtomicCSubNoRtnInsts] in
895-
def : DSAtomicRetPat<noRetInst, vt,
896-
!cast<PatFrag>(frag#"_noret_local_addrspace"), /* complexity */ 1>;
893+
def : DSAtomicRetPat<noRetInst, vt,
894+
!cast<PatFrag>(frag#"_noret_local_addrspace"), /* complexity */ 1>;
897895
}
898896

899897
defm : DSAtomicRetNoRetPatIntrinsic_mc<DS_COND_SUB_RTN_U32, DS_COND_SUB_U32, i32, "int_amdgcn_atomic_cond_sub_u32">;
@@ -1279,6 +1277,14 @@ defm : DSAtomicRetNoRetPat_NoM0_mc<DS_PK_ADD_RTN_F16, DS_PK_ADD_F16, v2f16, "ato
12791277
defm : DSAtomicRetNoRetPat_NoM0_mc<DS_PK_ADD_RTN_BF16, DS_PK_ADD_BF16, v2bf16, "atomic_load_fadd">;
12801278
}
12811279

1280+
let SubtargetPredicate = HasAtomicDsCondSubClampInsts in {
1281+
1282+
defm : DSAtomicRetNoRetPat_NoM0_mc<DS_COND_SUB_RTN_U32, DS_COND_SUB_U32, i32, "atomic_load_usub_cond">;
1283+
1284+
defm : DSAtomicRetNoRetPat_NoM0_mc<DS_SUB_CLAMP_RTN_U32, DS_SUB_CLAMP_U32, i32, "atomic_load_usub_sat">;
1285+
1286+
} // let SubtargetPredicate = HasAtomicDsCondSubClampInsts
1287+
12821288
let SubtargetPredicate = isGFX6GFX7GFX8GFX9GFX10 in {
12831289
defm : DSAtomicCmpXChgSwapped_mc<DS_CMPST_RTN_B32, DS_CMPST_B32, i32, "atomic_cmp_swap">;
12841290
}

‎llvm/lib/Target/AMDGPU/FLATInstructions.td‎

Lines changed: 9 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2179,6 +2179,11 @@ defm : FlatAtomicPat <"FLAT_ATOMIC_MIN_F64", "atomic_load_fmin_"#as, f64>;
21792179
defm : FlatAtomicPat <"FLAT_ATOMIC_MAX_F64", "atomic_load_fmax_"#as, f64>;
21802180
}
21812181

2182+
let SubtargetPredicate = HasAtomicCondSubClampFlatInsts in {
2183+
defm : FlatAtomicRtnPat<"FLAT_ATOMIC_COND_SUB_U32", "atomic_load_usub_cond_" #as, i32 >;
2184+
2185+
defm : FlatAtomicNoRtnPat<"FLAT_ATOMIC_COND_SUB_U32", "atomic_load_usub_cond_"#as, i32>;
2186+
}
21822187
} // end foreach as
21832188

21842189
defm : FlatStorePats <FLAT_STORE_BYTE, truncstorei8_flat, i16>;
@@ -2350,10 +2355,10 @@ defm : GlobalFLATAtomicPats <"GLOBAL_ATOMIC_OR", "atomic_load_or_global", i32>;
23502355
defm : GlobalFLATAtomicPats <"GLOBAL_ATOMIC_SWAP", "atomic_swap_global", i32>;
23512356
defm : GlobalFLATAtomicPats <"GLOBAL_ATOMIC_CMPSWAP", "AMDGPUatomic_cmp_swap_global", i32, v2i32>;
23522357
defm : GlobalFLATAtomicPats <"GLOBAL_ATOMIC_XOR", "atomic_load_xor_global", i32>;
2353-
defm : GlobalFLATAtomicPatsRtn <"GLOBAL_ATOMIC_CSUB", "int_amdgcn_global_atomic_csub", i32, i32, /* isIntr */ 1>;
2358+
defm : GlobalFLATAtomicPatsRtn <"GLOBAL_ATOMIC_CSUB", "atomic_load_usub_sat_global", i32>;
23542359

23552360
let SubtargetPredicate = HasAtomicCSubNoRtnInsts in
2356-
defm : GlobalFLATAtomicPatsNoRtn <"GLOBAL_ATOMIC_CSUB", "int_amdgcn_global_atomic_csub", i32, i32, /* isIntr */ 1>;
2361+
defm : GlobalFLATAtomicPatsNoRtn <"GLOBAL_ATOMIC_CSUB", "atomic_load_usub_sat_global", i32>;
23572362

23582363
defm : GlobalFLATAtomicPats <"GLOBAL_ATOMIC_ADD_X2", "atomic_load_add_global", i64>;
23592364
defm : GlobalFLATAtomicPats <"GLOBAL_ATOMIC_SUB_X2", "atomic_load_sub_global", i64>;
@@ -2370,10 +2375,8 @@ defm : GlobalFLATAtomicPats <"GLOBAL_ATOMIC_CMPSWAP_X2", "AMDGPUatomic_cmp_swap_
23702375
defm : GlobalFLATAtomicPats <"GLOBAL_ATOMIC_XOR_X2", "atomic_load_xor_global", i64>;
23712376

23722377
let SubtargetPredicate = isGFX12Plus in {
2373-
defm : GlobalFLATAtomicPatsRtnWithAddrSpace <"GLOBAL_ATOMIC_COND_SUB_U32", "int_amdgcn_atomic_cond_sub_u32", "global_addrspace", i32>;
2374-
2375-
let SubtargetPredicate = HasAtomicCSubNoRtnInsts in
2376-
defm : GlobalFLATAtomicPatsNoRtnWithAddrSpace <"GLOBAL_ATOMIC_COND_SUB_U32", "int_amdgcn_atomic_cond_sub_u32", "global_addrspace", i32>;
2378+
defm : GlobalFLATAtomicPatsRtn <"GLOBAL_ATOMIC_COND_SUB_U32", "atomic_load_usub_cond_global", i32>;
2379+
defm : GlobalFLATAtomicPatsNoRtn <"GLOBAL_ATOMIC_COND_SUB_U32", "atomic_load_usub_cond_global", i32>;
23772380
}
23782381

23792382
let OtherPredicates = [isGFX12PlusNot12_50] in

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