Update llvm/test/CodeGen/RISCV/rv64i-shift-sext.ll

topperc · web-flow · commit 74138a9c862d · 2025-08-26T23:43:03.000-07:00
diff --git a/llvm/test/CodeGen/RISCV/rv64i-shift-sext.ll b/llvm/test/CodeGen/RISCV/rv64i-shift-sext.ll
@@ -221,7 +221,7 @@ define signext i32 @test14(ptr %0, ptr %1, i64 %2) {
   ret i32 %12
 }
 
-; Test that we can propage sign bits through sraw. We should use an slli
+; Test that we can propagate sign bits through sraw. We should use an slli
 ; instead of slliw.
 define signext i32 @test15(i32 signext %x, i32 signext %y) {
 ; RV64I-LABEL: test15:

Original file line number	Diff line number	Diff line change
`@@ -221,7 +221,7 @@ define signext i32 @test14(ptr %0, ptr %1, i64 %2) {`
`221`	`221`	`ret i32 %12`
`222`	`222`	`}`
`223`	`223`
`224`		`-; Test that we can propage sign bits through sraw. We should use an slli`
	`224`	`+; Test that we can propagate sign bits through sraw. We should use an slli`
`225`	`225`	`; instead of slliw.`
`226`	`226`	`define signext i32 @test15(i32 signext %x, i32 signext %y) {`
`227`	`227`	`; RV64I-LABEL: test15:`