@@ -245,7 +245,7 @@ class SIFoldOperandsImpl {
245245 std::optional<int64_t > getImmOrMaterializedImm (MachineOperand &Op) const ;
246246 bool tryConstantFoldOp (MachineInstr *MI) const ;
247247 bool tryFoldCndMask (MachineInstr &MI) const ;
248- bool tryFoldArithmetic (MachineInstr &MI) const ;
248+ bool tryFoldZeroHighBits (MachineInstr &MI) const ;
249249 bool foldInstOperand (MachineInstr &MI, const FoldableDef &OpToFold) const ;
250250
251251 bool foldCopyToAGPRRegSequence (MachineInstr *CopyMI) const ;
@@ -1730,33 +1730,26 @@ bool SIFoldOperandsImpl::tryFoldCndMask(MachineInstr &MI) const {
17301730 return true ;
17311731}
17321732
1733- bool SIFoldOperandsImpl::tryFoldArithmetic (MachineInstr &MI) const {
1734- unsigned Opc = MI.getOpcode ();
1735-
1736- switch (Opc) {
1737- default :
1738- return false ;
1739- case AMDGPU::V_AND_B32_e64:
1740- case AMDGPU::V_AND_B32_e32: {
1741- std::optional<int64_t > Src0Imm = getImmOrMaterializedImm (MI.getOperand (1 ));
1742- if (!Src0Imm || *Src0Imm != 0xffff || !MI.getOperand (2 ).isReg ())
1743- return false ;
1733+ bool SIFoldOperandsImpl::tryFoldZeroHighBits (MachineInstr &MI) const {
1734+ if (MI.getOpcode () != AMDGPU::V_AND_B32_e64 &&
1735+ MI.getOpcode () != AMDGPU::V_AND_B32_e32)
1736+ return false ;
17441737
1745- Register Src1 = MI.getOperand (2 ).getReg ();
1746- MachineInstr *SrcDef = MRI->getVRegDef (Src1);
1747- if (!ST->zeroesHigh16BitsOfDest (SrcDef->getOpcode ()))
1748- return false ;
1738+ std::optional<int64_t > Src0Imm = getImmOrMaterializedImm (MI.getOperand (1 ));
1739+ if (!Src0Imm || *Src0Imm != 0xffff || !MI.getOperand (2 ).isReg ())
1740+ return false ;
17491741
1750- Register Dst = MI.getOperand (0 ).getReg ();
1751- MRI->replaceRegWith (Dst, Src1);
1752- if (!MI.getOperand (2 ).isKill ())
1753- MRI->clearKillFlags (Src1);
1754- MI.eraseFromParent ();
1755- return true ;
1756- }
1757- }
1742+ Register Src1 = MI.getOperand (2 ).getReg ();
1743+ MachineInstr *SrcDef = MRI->getVRegDef (Src1);
1744+ if (!ST->zeroesHigh16BitsOfDest (SrcDef->getOpcode ()))
1745+ return false ;
17581746
1759- return false ;
1747+ Register Dst = MI.getOperand (0 ).getReg ();
1748+ MRI->replaceRegWith (Dst, Src1);
1749+ if (!MI.getOperand (2 ).isKill ())
1750+ MRI->clearKillFlags (Src1);
1751+ MI.eraseFromParent ();
1752+ return true ;
17601753}
17611754
17621755bool SIFoldOperandsImpl::foldInstOperand (MachineInstr &MI,
@@ -2797,7 +2790,7 @@ bool SIFoldOperandsImpl::run(MachineFunction &MF) {
27972790 for (auto &MI : make_early_inc_range (*MBB)) {
27982791 Changed |= tryFoldCndMask (MI);
27992792
2800- if (tryFoldArithmetic (MI)) {
2793+ if (tryFoldZeroHighBits (MI)) {
28012794 Changed = true ;
28022795 continue ;
28032796 }
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