@@ -2199,14 +2199,9 @@ void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
21992199 // Emit a store of the return value through the virtual register.
22002200 // Leave Outs empty so that LowerReturn won't try to load return
22012201 // registers the usual way.
2202- SmallVector<EVT, 1> PtrValueVTs;
2203- ComputeValueVTs(TLI, DL,
2204- PointerType::get(F->getContext(),
2205- DAG.getDataLayout().getAllocaAddrSpace()),
2206- PtrValueVTs);
2207-
2202+ MVT PtrValueVT = TLI.getPointerTy (DL, DL.getAllocaAddrSpace ());
22082203 SDValue RetPtr =
2209- DAG.getCopyFromReg(Chain, getCurSDLoc(), DemoteReg, PtrValueVTs[0] );
2204+ DAG.getCopyFromReg (Chain, getCurSDLoc (), DemoteReg, PtrValueVT );
22102205 SDValue RetOp = getValue (I.getOperand (0 ));
22112206
22122207 SmallVector<EVT, 4 > ValueVTs, MemVTs;
@@ -11309,13 +11304,7 @@ TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
1130911304 if (!CanLowerReturn) {
1131011305 // The instruction result is the result of loading from the
1131111306 // hidden sret parameter.
11312- SmallVector<EVT, 1> PVTs;
11313- Type *PtrRetTy =
11314- PointerType::get(OrigRetTy->getContext(), DL.getAllocaAddrSpace());
11315-
11316- ComputeValueVTs(*this, DL, PtrRetTy, PVTs);
11317- assert(PVTs.size() == 1 && "Pointers should fit in one register");
11318- EVT PtrVT = PVTs[0];
11307+ MVT PtrVT = getPointerTy (DL, DL.getAllocaAddrSpace ());
1131911308
1132011309 unsigned NumValues = RetTys.size ();
1132111310 ReturnValues.resize (NumValues);
@@ -11635,18 +11624,12 @@ void SelectionDAGISel::LowerArguments(const Function &F) {
1163511624
1163611625 if (!FuncInfo->CanLowerReturn ) {
1163711626 // Put in an sret pointer parameter before all the other parameters.
11638- SmallVector<EVT, 1> ValueVTs;
11639- ComputeValueVTs(*TLI, DAG.getDataLayout(),
11640- PointerType::get(F.getContext(),
11641- DAG.getDataLayout().getAllocaAddrSpace()),
11642- ValueVTs);
11643-
11644- // NOTE: Assuming that a pointer will never break down to more than one VT
11645- // or one register.
11627+ MVT ValueVT = TLI->getPointerTy (DL, DL.getAllocaAddrSpace ());
11628+
1164611629 ISD::ArgFlagsTy Flags;
1164711630 Flags.setSRet ();
11648- MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0] );
11649- ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0] , true,
11631+ MVT RegisterVT = TLI->getRegisterType (*DAG.getContext (), ValueVT );
11632+ ISD::InputArg RetArg (Flags, RegisterVT, ValueVT , true ,
1165011633 ISD::InputArg::NoArgIndex, 0 );
1165111634 Ins.push_back (RetArg);
1165211635 }
@@ -11829,12 +11812,7 @@ void SelectionDAGISel::LowerArguments(const Function &F) {
1182911812 if (!FuncInfo->CanLowerReturn ) {
1183011813 // Create a virtual register for the sret pointer, and put in a copy
1183111814 // from the sret argument into it.
11832- SmallVector<EVT, 1> ValueVTs;
11833- ComputeValueVTs(*TLI, DAG.getDataLayout(),
11834- PointerType::get(F.getContext(),
11835- DAG.getDataLayout().getAllocaAddrSpace()),
11836- ValueVTs);
11837- MVT VT = ValueVTs[0].getSimpleVT();
11815+ MVT VT = TLI->getPointerTy (DL, DL.getAllocaAddrSpace ());
1183811816 MVT RegVT = TLI->getRegisterType (*CurDAG->getContext (), VT);
1183911817 std::optional<ISD::NodeType> AssertOp;
1184011818 SDValue ArgValue =
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