Support i16 to i32 case

Author: ecnelises

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

@@ -14436,20 +14436,44 @@ SDValue PPCTargetLowering::combineSetCC(SDNode *N, DAGCombinerInfo &DCI) const {
     }
   }
 
-  // Combine (a-2^(M-1)) => sext(trunc(a, M), 64)
-  if (CC == ISD::SETULT && LHS.getOpcode() == ISD::ADD && OpVT == MVT::i64 &&
-      isa<ConstantSDNode>(RHS) && isa<ConstantSDNode>(LHS.getOperand(1))) {
-    uint64_t ShiftVal =
-        ~(cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) + 1;
-    uint64_t CmpVal = ~(cast<ConstantSDNode>(RHS)->getZExtValue()) + 1;
-    if (isPowerOf2_64(ShiftVal) && ShiftVal << 1 == CmpVal) {
-      unsigned DestBits = Log2_64(CmpVal);
-      if (DestBits == 8 || DestBits == 16 || DestBits == 32) {
-        SDValue Conv =
-            DAG.getSExtOrTrunc(DAG.getSExtOrTrunc(LHS.getOperand(0), DL,
-                                                  MVT::getIntegerVT(DestBits)),
-                               DL, OpVT);
-        return DAG.getSetCC(DL, VT, LHS.getOperand(0), Conv, ISD::SETNE);
+  if (CC == ISD::SETULT && isa<ConstantSDNode>(RHS)) {
+    uint64_t RHSVal = cast<ConstantSDNode>(RHS)->getZExtValue();
+    if (LHS.getOpcode() == ISD::ADD && isa<ConstantSDNode>(LHS.getOperand(1))) {
+      uint64_t Addend = cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue();
+      if (OpVT == MVT::i64) {
+        // (a-2^(M-1)) => sext(trunc(a, M), 64)
+        uint64_t ShiftVal = ~Addend + 1;
+        uint64_t CmpVal = ~RHSVal + 1;
+        if (isPowerOf2_64(ShiftVal) && ShiftVal << 1 == CmpVal) {
+          unsigned DestBits = Log2_64(CmpVal);
+          if (DestBits == 8 || DestBits == 16 || DestBits == 32) {
+            SDValue Conv = DAG.getSExtOrTrunc(
+                DAG.getSExtOrTrunc(LHS.getOperand(0), DL,
+                                   MVT::getIntegerVT(DestBits)),
+                DL, OpVT);
+            return DAG.getSetCC(DL, VT, LHS.getOperand(0), Conv, ISD::SETNE);
+          }
+        }
+      } else if (OpVT == MVT::i32) {
+        if (RHSVal == 0xffffff00 && Addend == 0xffffff80) {
+          SDValue Conv = DAG.getSExtOrTrunc(
+              DAG.getSExtOrTrunc(LHS.getOperand(0), DL, MVT::i8), DL, OpVT);
+          return DAG.getSetCC(DL, VT, LHS.getOperand(0), Conv, ISD::SETNE);
+        }
+      }
+    } else if (LHS.getOpcode() == ISD::SRL &&
+               LHS.getOperand(0).getOpcode() == ISD::ADD &&
+               isa<ConstantSDNode>(LHS.getOperand(1)) &&
+               isa<ConstantSDNode>(LHS.getOperand(0).getOperand(1))) {
+      if (RHSVal == 65535 &&
+          cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() == 16 &&
+          cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))
+                  ->getZExtValue() == 0xffff8000) {
+        SDValue Conv = DAG.getSExtOrTrunc(
+            DAG.getSExtOrTrunc(LHS.getOperand(0).getOperand(0), DL, MVT::i16),
+            DL, OpVT);
+        return DAG.getSetCC(DL, VT, LHS.getOperand(0).getOperand(0), Conv,
+                            ISD::SETNE);
       }
     }
   }

llvm/test/CodeGen/PowerPC/setcc-to-sub.ll

@@ -134,12 +134,11 @@ entry:
 define zeroext i1 @test8(i32 %a) {
 ; CHECK-LABEL: test8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addi 3, 3, -32768
-; CHECK-NEXT:    lis 4, -1
-; CHECK-NEXT:    rlwinm 3, 3, 16, 16, 31
-; CHECK-NEXT:    ori 4, 4, 1
-; CHECK-NEXT:    add 3, 3, 4
-; CHECK-NEXT:    rldicl 3, 3, 1, 63
+; CHECK-NEXT:    extsh 4, 3
+; CHECK-NEXT:    xor 3, 3, 4
+; CHECK-NEXT:    cntlzw 3, 3
+; CHECK-NEXT:    srwi 3, 3, 5
+; CHECK-NEXT:    xori 3, 3, 1
 ; CHECK-NEXT:    blr
 entry:
   %0 = add i32 %a, -32768
@@ -150,13 +149,11 @@ entry:
 define zeroext i1 @test9(i32 %a) {
 ; CHECK-LABEL: test9:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lis 4, -256
-; CHECK-NEXT:    addi 3, 3, -128
-; CHECK-NEXT:    ori 4, 4, 1
-; CHECK-NEXT:    clrldi 3, 3, 32
-; CHECK-NEXT:    rldic 4, 4, 8, 0
-; CHECK-NEXT:    add 3, 3, 4
-; CHECK-NEXT:    rldicl 3, 3, 1, 63
+; CHECK-NEXT:    extsb 4, 3
+; CHECK-NEXT:    xor 3, 3, 4
+; CHECK-NEXT:    cntlzw 3, 3
+; CHECK-NEXT:    srwi 3, 3, 5
+; CHECK-NEXT:    xori 3, 3, 1
 ; CHECK-NEXT:    blr
 entry:
   %0 = add i32 %a, -128