fix fails and cleanup

RolandF77 · RolandF77 · commit 7497b0c8ce1a · 2025-04-15T18:25:49.000Z
diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
@@ -135,10 +135,6 @@ MCRegister PPC::getRegNumForOperand(const MCInstrDesc &Desc, MCRegister Reg,
       if (PPC::isVRRegister(Reg))
 	return PPC::VSX32 + (Reg - PPC::V0);
       break;
-    case PPC::DMRROWpRCRegClassID: {
-      // Reference to dmr reg. There are four dmrrow pairs per dmr.
-      return PPC::DMR0 + ((Reg - PPC::DMRROWp0) / 4);
-    }
     // Other RegClass doesn't need mapping
     default:
       break;
diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
@@ -294,6 +294,10 @@ static inline bool isVFRegister(unsigned Reg) {
 static inline bool isVRRegister(unsigned Reg) {
   return Reg >= PPC::V0 && Reg <= PPC::V31;
 }
+
+static inline bool isDMRROWpRegister(unsigned Reg) {
+  return Reg >= PPC::DMRROWp0 && Reg <= PPC::DMRROWp31;
+}
 } // namespace PPC
 } // namespace llvm
 
diff --git a/llvm/lib/Target/PowerPC/PPCMCInstLower.cpp b/llvm/lib/Target/PowerPC/PPCMCInstLower.cpp
@@ -196,6 +196,12 @@ bool llvm::LowerPPCMachineOperandToMCOperand(const MachineOperand &MO,
     assert(MO.getReg() > PPC::NoRegister &&
            MO.getReg() < PPC::NUM_TARGET_REGS &&
            "Invalid register for this target!");
+    // ISA instructions refer to the containing dmr reg.
+    if (PPC::isDMRROWpRegister(MO.getReg())) {
+      OutMO =
+          MCOperand::createReg(PPC::DMR0 + (MO.getReg() - PPC::DMRROWp0) / 4);
+      return true;
+    }
     // Ignore all implicit register operands.
     if (MO.isImplicit())
       return false;
diff --git a/llvm/test/CodeGen/PowerPC/dmr-enable.ll b/llvm/test/CodeGen/PowerPC/dmr-enable.ll
@@ -166,33 +166,33 @@ define void @text256(ptr %vp1, ptr %rp1, ptr %rp2, ptr %rp3, ptr %rp4)  {
 ; CHECK-LABEL: text256:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    dmsetdmrz dmr0
-; CHECK-NEXT:    dmxxextfdmr256 vsp34, dmrrowp0, 0
+; CHECK-NEXT:    dmxxextfdmr256 vsp34, dmr0, 0
 ; CHECK-NEXT:    stxv v2, 16(r4)
 ; CHECK-NEXT:    stxv v3, 0(r4)
-; CHECK-NEXT:    dmxxextfdmr256 vsp34, dmrrowp1, 1
+; CHECK-NEXT:    dmxxextfdmr256 vsp34, dmr0, 1
 ; CHECK-NEXT:    stxv v2, 16(r5)
 ; CHECK-NEXT:    stxv v3, 0(r5)
-; CHECK-NEXT:    dmxxextfdmr256 vsp34, dmrrowp2, 2
+; CHECK-NEXT:    dmxxextfdmr256 vsp34, dmr0, 2
 ; CHECK-NEXT:    stxv v2, 16(r6)
 ; CHECK-NEXT:    stxv v3, 0(r6)
-; CHECK-NEXT:    dmxxextfdmr256 vsp34, dmrrowp3, 3
+; CHECK-NEXT:    dmxxextfdmr256 vsp34, dmr0, 3
 ; CHECK-NEXT:    stxv v2, 16(r7)
 ; CHECK-NEXT:    stxv v3, 0(r7)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: text256:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    dmsetdmrz dmr0
-; CHECK-BE-NEXT:    dmxxextfdmr256 vsp34, dmrrowp0, 0
+; CHECK-BE-NEXT:    dmxxextfdmr256 vsp34, dmr0, 0
 ; CHECK-BE-NEXT:    stxv v3, 16(r4)
 ; CHECK-BE-NEXT:    stxv v2, 0(r4)
-; CHECK-BE-NEXT:    dmxxextfdmr256 vsp34, dmrrowp1, 1
+; CHECK-BE-NEXT:    dmxxextfdmr256 vsp34, dmr0, 1
 ; CHECK-BE-NEXT:    stxv v3, 16(r5)
 ; CHECK-BE-NEXT:    stxv v2, 0(r5)
-; CHECK-BE-NEXT:    dmxxextfdmr256 vsp34, dmrrowp2, 2
+; CHECK-BE-NEXT:    dmxxextfdmr256 vsp34, dmr0, 2
 ; CHECK-BE-NEXT:    stxv v3, 16(r6)
 ; CHECK-BE-NEXT:    stxv v2, 0(r6)
-; CHECK-BE-NEXT:    dmxxextfdmr256 vsp34, dmrrowp3, 3
+; CHECK-BE-NEXT:    dmxxextfdmr256 vsp34, dmr0, 3
 ; CHECK-BE-NEXT:    stxv v3, 16(r7)
 ; CHECK-BE-NEXT:    stxv v2, 0(r7)
 ; CHECK-BE-NEXT:    blr
@@ -282,7 +282,7 @@ define void @tins256(ptr %vp1, ptr %vp2, ptr %vp3, ptr %vp4, ptr %rp1, ptr %rp2,
 ; CHECK-NEXT:    lxv v2, 16(r3)
 ; CHECK-NEXT:    lxv v3, 0(r3)
 ; CHECK-NEXT:    dmsetdmrz dmr0
-; CHECK-NEXT:    dmxxinstdmr256 dmrrowp0, vsp34, 0
+; CHECK-NEXT:    dmxxinstdmr256 dmr0, vsp34, 0
 ; CHECK-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 0
 ; CHECK-NEXT:    stxvp vsp34, 96(r7)
 ; CHECK-NEXT:    stxvp vsp36, 64(r7)
@@ -291,21 +291,21 @@ define void @tins256(ptr %vp1, ptr %vp2, ptr %vp3, ptr %vp4, ptr %rp1, ptr %rp2,
 ; CHECK-NEXT:    stxvp vsp36, 0(r7)
 ; CHECK-NEXT:    lxv v2, 16(r4)
 ; CHECK-NEXT:    lxv v3, 0(r4)
-; CHECK-NEXT:    dmxxinstdmr256 dmrrowp1, vsp34, 1
+; CHECK-NEXT:    dmxxinstdmr256 dmr0, vsp34, 1
 ; CHECK-NEXT:    dmxxextfdmr512 vsp36, vsp32, wacc0, 0
 ; CHECK-NEXT:    stxvp vsp36, 96(r8)
 ; CHECK-NEXT:    stxvp vsp32, 64(r8)
 ; CHECK-NEXT:    dmxxextfdmr512 vsp36, vsp32, wacc_hi0, 1
 ; CHECK-NEXT:    stxvp vsp36, 32(r8)
 ; CHECK-NEXT:    stxvp vsp32, 0(r8)
-; CHECK-NEXT:    dmxxinstdmr256 dmrrowp2, vsp34, 2
+; CHECK-NEXT:    dmxxinstdmr256 dmr0, vsp34, 2
 ; CHECK-NEXT:    dmxxextfdmr512 vsp36, vsp32, wacc0, 0
 ; CHECK-NEXT:    stxvp vsp36, 96(r9)
 ; CHECK-NEXT:    stxvp vsp32, 64(r9)
 ; CHECK-NEXT:    dmxxextfdmr512 vsp36, vsp32, wacc_hi0, 1
 ; CHECK-NEXT:    stxvp vsp36, 32(r9)
 ; CHECK-NEXT:    stxvp vsp32, 0(r9)
-; CHECK-NEXT:    dmxxinstdmr256 dmrrowp3, vsp34, 3
+; CHECK-NEXT:    dmxxinstdmr256 dmr0, vsp34, 3
 ; CHECK-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 0
 ; CHECK-NEXT:    stxvp vsp34, 96(r10)
 ; CHECK-NEXT:    stxvp vsp36, 64(r10)
@@ -319,7 +319,7 @@ define void @tins256(ptr %vp1, ptr %vp2, ptr %vp3, ptr %vp4, ptr %rp1, ptr %rp2,
 ; CHECK-BE-NEXT:    lxv v2, 0(r3)
 ; CHECK-BE-NEXT:    lxv v3, 16(r3)
 ; CHECK-BE-NEXT:    dmsetdmrz dmr0
-; CHECK-BE-NEXT:    dmxxinstdmr256 dmrrowp0, vsp34, 0
+; CHECK-BE-NEXT:    dmxxinstdmr256 dmr0, vsp34, 0
 ; CHECK-BE-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
 ; CHECK-BE-NEXT:    stxvp vsp36, 96(r7)
 ; CHECK-BE-NEXT:    stxvp vsp34, 64(r7)
@@ -328,21 +328,21 @@ define void @tins256(ptr %vp1, ptr %vp2, ptr %vp3, ptr %vp4, ptr %rp1, ptr %rp2,
 ; CHECK-BE-NEXT:    stxvp vsp34, 0(r7)
 ; CHECK-BE-NEXT:    lxv v2, 0(r4)
 ; CHECK-BE-NEXT:    lxv v3, 16(r4)
-; CHECK-BE-NEXT:    dmxxinstdmr256 dmrrowp1, vsp34, 1
+; CHECK-BE-NEXT:    dmxxinstdmr256 dmr0, vsp34, 1
 ; CHECK-BE-NEXT:    dmxxextfdmr512 vsp36, vsp32, wacc_hi0, 1
 ; CHECK-BE-NEXT:    stxvp vsp32, 96(r8)
 ; CHECK-BE-NEXT:    stxvp vsp36, 64(r8)
 ; CHECK-BE-NEXT:    dmxxextfdmr512 vsp36, vsp32, wacc0, 0
 ; CHECK-BE-NEXT:    stxvp vsp32, 32(r8)
 ; CHECK-BE-NEXT:    stxvp vsp36, 0(r8)
-; CHECK-BE-NEXT:    dmxxinstdmr256 dmrrowp2, vsp34, 2
+; CHECK-BE-NEXT:    dmxxinstdmr256 dmr0, vsp34, 2
 ; CHECK-BE-NEXT:    dmxxextfdmr512 vsp36, vsp32, wacc_hi0, 1
 ; CHECK-BE-NEXT:    stxvp vsp32, 96(r9)
 ; CHECK-BE-NEXT:    stxvp vsp36, 64(r9)
 ; CHECK-BE-NEXT:    dmxxextfdmr512 vsp36, vsp32, wacc0, 0
 ; CHECK-BE-NEXT:    stxvp vsp32, 32(r9)
 ; CHECK-BE-NEXT:    stxvp vsp36, 0(r9)
-; CHECK-BE-NEXT:    dmxxinstdmr256 dmrrowp3, vsp34, 3
+; CHECK-BE-NEXT:    dmxxinstdmr256 dmr0, vsp34, 3
 ; CHECK-BE-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
 ; CHECK-BE-NEXT:    stxvp vsp36, 96(r10)
 ; CHECK-BE-NEXT:    stxvp vsp34, 64(r10)
