Skip to content

Commit 74b7651

Browse files
LiqinWengLiqinWeng
committed
[LV][EVL] Support cast instruction with EVL-vectorization
1 parent 5d08625 commit 74b7651

File tree

7 files changed

+367
-15
lines changed

7 files changed

+367
-15
lines changed

‎llvm/lib/Transforms/Vectorize/LoopVectorize.cpp‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4455,6 +4455,7 @@ static bool willGenerateVectors(VPlan &Plan, ElementCount VF,
44554455
case VPDef::VPWidenCallSC:
44564456
case VPDef::VPWidenCanonicalIVSC:
44574457
case VPDef::VPWidenCastSC:
4458+
case VPDef::VPWidenCastEVLSC:
44584459
case VPDef::VPWidenGEPSC:
44594460
case VPDef::VPWidenIntrinsicSC:
44604461
case VPDef::VPWidenSC:

‎llvm/lib/Transforms/Vectorize/VPlan.h‎

Lines changed: 72 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -905,6 +905,7 @@ class VPSingleDefRecipe : public VPRecipeBase, public VPValue {
905905
case VPRecipeBase::VPWidenCallSC:
906906
case VPRecipeBase::VPWidenCanonicalIVSC:
907907
case VPRecipeBase::VPWidenCastSC:
908+
case VPRecipeBase::VPWidenCastEVLSC:
908909
case VPRecipeBase::VPWidenGEPSC:
909910
case VPRecipeBase::VPWidenIntrinsicSC:
910911
case VPRecipeBase::VPWidenSC:
@@ -1106,6 +1107,7 @@ class VPRecipeWithIRFlags : public VPSingleDefRecipe {
11061107
R->getVPDefID() == VPRecipeBase::VPWidenEVLSC ||
11071108
R->getVPDefID() == VPRecipeBase::VPWidenGEPSC ||
11081109
R->getVPDefID() == VPRecipeBase::VPWidenCastSC ||
1110+
R->getVPDefID() == VPRecipeBase::VPWidenCastEVLSC ||
11091111
R->getVPDefID() == VPRecipeBase::VPReplicateSC ||
11101112
R->getVPDefID() == VPRecipeBase::VPVectorPointerSC;
11111113
}
@@ -1571,19 +1573,28 @@ class VPWidenCastRecipe : public VPRecipeWithIRFlags {
15711573
/// Result type for the cast.
15721574
Type *ResultTy;
15731575

1574-
public:
1575-
VPWidenCastRecipe(Instruction::CastOps Opcode, VPValue *Op, Type *ResultTy,
1576-
CastInst &UI)
1576+
protected:
1577+
VPWidenCastRecipe(unsigned VPDefOpcode, Instruction::CastOps Opcode,
1578+
VPValue *Op, Type *ResultTy, CastInst &UI)
15771579
: VPRecipeWithIRFlags(VPDef::VPWidenCastSC, Op, UI), Opcode(Opcode),
15781580
ResultTy(ResultTy) {
15791581
assert(UI.getOpcode() == Opcode &&
15801582
"opcode of underlying cast doesn't match");
15811583
}
15821584

1583-
VPWidenCastRecipe(Instruction::CastOps Opcode, VPValue *Op, Type *ResultTy)
1585+
VPWidenCastRecipe(unsigned VPDefOpcode, Instruction::CastOps Opcode,
1586+
VPValue *Op, Type *ResultTy)
15841587
: VPRecipeWithIRFlags(VPDef::VPWidenCastSC, Op), Opcode(Opcode),
15851588
ResultTy(ResultTy) {}
15861589

1590+
public:
1591+
VPWidenCastRecipe(Instruction::CastOps Opcode, VPValue *Op, Type *ResultTy,
1592+
CastInst &UI)
1593+
: VPWidenCastRecipe(VPDef::VPWidenCastSC, Opcode, Op, ResultTy, UI) {}
1594+
1595+
VPWidenCastRecipe(Instruction::CastOps Opcode, VPValue *Op, Type *ResultTy)
1596+
: VPWidenCastRecipe(VPDef::VPWidenCastSC, Opcode, Op, ResultTy) {}
1597+
15871598
~VPWidenCastRecipe() override = default;
15881599

15891600
VPWidenCastRecipe *clone() override {
@@ -1594,7 +1605,15 @@ class VPWidenCastRecipe : public VPRecipeWithIRFlags {
15941605
return new VPWidenCastRecipe(Opcode, getOperand(0), ResultTy);
15951606
}
15961607

1597-
VP_CLASSOF_IMPL(VPDef::VPWidenCastSC)
1608+
static inline bool classof(const VPRecipeBase *R) {
1609+
return R->getVPDefID() == VPRecipeBase::VPWidenCastSC ||
1610+
R->getVPDefID() == VPRecipeBase::VPWidenCastEVLSC;
1611+
}
1612+
1613+
static inline bool classof(const VPUser *U) {
1614+
auto *R = dyn_cast<VPRecipeBase>(U);
1615+
return R && classof(R);
1616+
}
15981617

15991618
/// Produce widened copies of the cast.
16001619
void execute(VPTransformState &State) override;
@@ -1611,6 +1630,54 @@ class VPWidenCastRecipe : public VPRecipeWithIRFlags {
16111630
Type *getResultType() const { return ResultTy; }
16121631
};
16131632

1633+
// A recipe for widening cast operation with vector-predication intrinsics with
1634+
/// explicit vector length (EVL).
1635+
class VPWidenCastEVLRecipe : public VPWidenCastRecipe {
1636+
using VPRecipeWithIRFlags::transferFlags;
1637+
1638+
public:
1639+
VPWidenCastEVLRecipe(Instruction::CastOps Opcode, VPValue *Op, Type *ResultTy,
1640+
VPValue &EVL)
1641+
: VPWidenCastRecipe(VPDef::VPWidenCastEVLSC, Opcode, Op, ResultTy) {
1642+
addOperand(&EVL);
1643+
}
1644+
VPWidenCastEVLRecipe(VPWidenCastRecipe &W, VPValue &EVL)
1645+
: VPWidenCastEVLRecipe(W.getOpcode(), W.getOperand(0), W.getResultType(),
1646+
EVL) {
1647+
transferFlags(W);
1648+
}
1649+
1650+
~VPWidenCastEVLRecipe() override = default;
1651+
1652+
VPWidenCastEVLRecipe *clone() final {
1653+
llvm_unreachable("VPWidenEVLRecipe cannot be cloned");
1654+
return nullptr;
1655+
}
1656+
1657+
VP_CLASSOF_IMPL(VPDef::VPWidenCastEVLSC)
1658+
1659+
VPValue *getEVL() { return getOperand(getNumOperands() - 1); }
1660+
const VPValue *getEVL() const { return getOperand(getNumOperands() - 1); }
1661+
1662+
/// Produce a vp-intrinsic copies of the cast.
1663+
void execute(VPTransformState &State) final;
1664+
1665+
/// Returns true if the recipe only uses the first lane of operand \p Op.
1666+
bool onlyFirstLaneUsed(const VPValue *Op) const override {
1667+
assert(is_contained(operands(), Op) &&
1668+
"Op must be an operand of the recipe");
1669+
// EVL in that recipe is always the last operand, thus any use before means
1670+
// the VPValue should be vectorized.
1671+
return getEVL() == Op;
1672+
}
1673+
1674+
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1675+
/// Print the recipe.
1676+
void print(raw_ostream &O, const Twine &Indent,
1677+
VPSlotTracker &SlotTracker) const final;
1678+
#endif
1679+
};
1680+
16141681
/// VPScalarCastRecipe is a recipe to create scalar cast instructions.
16151682
class VPScalarCastRecipe : public VPSingleDefRecipe {
16161683
Instruction::CastOps Opcode;

‎llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp‎

Lines changed: 47 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -90,6 +90,7 @@ bool VPRecipeBase::mayWriteToMemory() const {
9090
case VPVectorPointerSC:
9191
case VPWidenCanonicalIVSC:
9292
case VPWidenCastSC:
93+
case VPWidenCastEVLSC:
9394
case VPWidenGEPSC:
9495
case VPWidenIntOrFpInductionSC:
9596
case VPWidenLoadEVLSC:
@@ -136,6 +137,7 @@ bool VPRecipeBase::mayReadFromMemory() const {
136137
case VPVectorPointerSC:
137138
case VPWidenCanonicalIVSC:
138139
case VPWidenCastSC:
140+
case VPWidenCastEVLSC:
139141
case VPWidenGEPSC:
140142
case VPWidenIntOrFpInductionSC:
141143
case VPWidenPHISC:
@@ -175,6 +177,7 @@ bool VPRecipeBase::mayHaveSideEffects() const {
175177
case VPVectorPointerSC:
176178
case VPWidenCanonicalIVSC:
177179
case VPWidenCastSC:
180+
case VPWidenCastEVLSC:
178181
case VPWidenGEPSC:
179182
case VPWidenIntOrFpInductionSC:
180183
case VPWidenPHISC:
@@ -1476,6 +1479,40 @@ void VPWidenCastRecipe::execute(VPTransformState &State) {
14761479
State.addMetadata(Cast, cast_or_null<Instruction>(getUnderlyingValue()));
14771480
}
14781481

1482+
void VPWidenCastEVLRecipe::execute(VPTransformState &State) {
1483+
unsigned Opcode = getOpcode();
1484+
State.setDebugLocFrom(getDebugLoc());
1485+
assert(State.UF == 1 && "Expected only UF == 1 when vectorizing with "
1486+
"explicit vector length.");
1487+
1488+
assert(State.get(getOperand(0), 0)->getType()->isVectorTy() &&
1489+
"VPWidenCastEVLRecipe should not be used for scalars");
1490+
1491+
// TODO: add more cast instruction, eg: fptoint/inttofp/inttoptr/fptofp
1492+
if (Opcode == Instruction::SExt || Opcode == Instruction::ZExt ||
1493+
Opcode == Instruction::Trunc) {
1494+
Value *SrcVal = State.get(getOperand(0), 0);
1495+
VectorType *SrcTy = cast<VectorType>(SrcVal->getType());
1496+
VectorType *DsType =
1497+
VectorType::get(getResultType(), SrcTy->getElementCount());
1498+
1499+
IRBuilderBase &BuilderIR = State.Builder;
1500+
VectorBuilder Builder(BuilderIR);
1501+
Value *Mask = BuilderIR.CreateVectorSplat(State.VF, BuilderIR.getTrue());
1502+
1503+
Builder.setMask(Mask).setEVL(State.get(getEVL(), 0, /*NeedsScalar=*/true));
1504+
Value *VPInst =
1505+
Builder.createVectorInstruction(Opcode, DsType, {SrcVal}, "vp.cast");
1506+
if (VPInst) {
1507+
if (auto *VecOp = dyn_cast<CastInst>(VPInst))
1508+
VecOp->copyIRFlags(getUnderlyingInstr());
1509+
}
1510+
State.set(this, VPInst, 0);
1511+
State.addMetadata(VPInst,
1512+
dyn_cast_or_null<Instruction>(getUnderlyingValue()));
1513+
}
1514+
}
1515+
14791516
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
14801517
void VPWidenCastRecipe::print(raw_ostream &O, const Twine &Indent,
14811518
VPSlotTracker &SlotTracker) const {
@@ -1486,6 +1523,16 @@ void VPWidenCastRecipe::print(raw_ostream &O, const Twine &Indent,
14861523
printOperands(O, SlotTracker);
14871524
O << " to " << *getResultType();
14881525
}
1526+
1527+
void VPWidenCastEVLRecipe::print(raw_ostream &O, const Twine &Indent,
1528+
VPSlotTracker &SlotTracker) const {
1529+
O << Indent << "WIDEN-VP ";
1530+
printAsOperand(O, SlotTracker);
1531+
O << " = vp." << Instruction::getOpcodeName(getOpcode()) << " ";
1532+
printFlags(O);
1533+
printOperands(O, SlotTracker);
1534+
O << " to " << *getResultType();
1535+
}
14891536
#endif
14901537

14911538
/// This function adds

‎llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1381,6 +1381,15 @@ static void transformRecipestoEVLRecipes(VPlan &Plan, VPValue &EVL) {
13811381
return nullptr;
13821382
return new VPWidenEVLRecipe(*W, EVL);
13831383
})
1384+
.Case<VPWidenCastRecipe>(
1385+
[&](VPWidenCastRecipe *W) -> VPRecipeBase * {
1386+
unsigned Opcode = W->getOpcode();
1387+
if (Opcode != Instruction::SExt &&
1388+
Opcode != Instruction::ZExt &&
1389+
Opcode != Instruction::Trunc)
1390+
return nullptr;
1391+
return new VPWidenCastEVLRecipe(*W, EVL);
1392+
})
13841393
.Case<VPReductionRecipe>([&](VPReductionRecipe *Red) {
13851394
VPValue *NewMask = GetNewMask(Red->getCondOp());
13861395
return new VPReductionEVLRecipe(*Red, EVL, NewMask);

‎llvm/lib/Transforms/Vectorize/VPlanValue.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -349,6 +349,7 @@ class VPDef {
349349
VPWidenCallSC,
350350
VPWidenCanonicalIVSC,
351351
VPWidenCastSC,
352+
VPWidenCastEVLSC,
352353
VPWidenGEPSC,
353354
VPWidenIntrinsicSC,
354355
VPWidenLoadEVLSC,

‎llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -159,38 +159,38 @@ define i32 @add_i16_i32(ptr nocapture readonly %x, i32 %n) {
159159
; IF-EVL-INLOOP: vector.body:
160160
; IF-EVL-INLOOP-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
161161
; IF-EVL-INLOOP-NEXT: [[EVL_BASED_IV:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], [[VECTOR_BODY]] ]
162-
; IF-EVL-INLOOP-NEXT: [[VEC_PHI:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[TMP12:%.*]], [[VECTOR_BODY]] ]
162+
; IF-EVL-INLOOP-NEXT: [[VEC_PHI:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[TMP11:%.*]], [[VECTOR_BODY]] ]
163163
; IF-EVL-INLOOP-NEXT: [[TMP5:%.*]] = sub i32 [[N]], [[EVL_BASED_IV]]
164164
; IF-EVL-INLOOP-NEXT: [[TMP6:%.*]] = call i32 @llvm.experimental.get.vector.length.i32(i32 [[TMP5]], i32 8, i1 true)
165165
; IF-EVL-INLOOP-NEXT: [[TMP7:%.*]] = add i32 [[EVL_BASED_IV]], 0
166166
; IF-EVL-INLOOP-NEXT: [[TMP8:%.*]] = getelementptr inbounds i16, ptr [[X:%.*]], i32 [[TMP7]]
167167
; IF-EVL-INLOOP-NEXT: [[TMP9:%.*]] = getelementptr inbounds i16, ptr [[TMP8]], i32 0
168168
; IF-EVL-INLOOP-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 8 x i16> @llvm.vp.load.nxv8i16.p0(ptr align 2 [[TMP9]], <vscale x 8 x i1> shufflevector (<vscale x 8 x i1> insertelement (<vscale x 8 x i1> poison, i1 true, i64 0), <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer), i32 [[TMP6]])
169-
; IF-EVL-INLOOP-NEXT: [[TMP10:%.*]] = sext <vscale x 8 x i16> [[VP_OP_LOAD]] to <vscale x 8 x i32>
170-
; IF-EVL-INLOOP-NEXT: [[TMP11:%.*]] = call i32 @llvm.vp.reduce.add.nxv8i32(i32 0, <vscale x 8 x i32> [[TMP10]], <vscale x 8 x i1> shufflevector (<vscale x 8 x i1> insertelement (<vscale x 8 x i1> poison, i1 true, i64 0), <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer), i32 [[TMP6]])
171-
; IF-EVL-INLOOP-NEXT: [[TMP12]] = add i32 [[TMP11]], [[VEC_PHI]]
169+
; IF-EVL-INLOOP-NEXT: [[VP_CAST:%.*]] = call <vscale x 8 x i32> @llvm.vp.sext.nxv8i32.nxv8i16(<vscale x 8 x i16> [[VP_OP_LOAD]], <vscale x 8 x i1> shufflevector (<vscale x 8 x i1> insertelement (<vscale x 8 x i1> poison, i1 true, i64 0), <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer), i32 [[TMP6]])
170+
; IF-EVL-INLOOP-NEXT: [[TMP10:%.*]] = call i32 @llvm.vp.reduce.add.nxv8i32(i32 0, <vscale x 8 x i32> [[VP_CAST]], <vscale x 8 x i1> shufflevector (<vscale x 8 x i1> insertelement (<vscale x 8 x i1> poison, i1 true, i64 0), <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer), i32 [[TMP6]])
171+
; IF-EVL-INLOOP-NEXT: [[TMP11]] = add i32 [[TMP10]], [[VEC_PHI]]
172172
; IF-EVL-INLOOP-NEXT: [[INDEX_EVL_NEXT]] = add i32 [[TMP6]], [[EVL_BASED_IV]]
173173
; IF-EVL-INLOOP-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], [[TMP4]]
174-
; IF-EVL-INLOOP-NEXT: [[TMP13:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
175-
; IF-EVL-INLOOP-NEXT: br i1 [[TMP13]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
174+
; IF-EVL-INLOOP-NEXT: [[TMP12:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
175+
; IF-EVL-INLOOP-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
176176
; IF-EVL-INLOOP: middle.block:
177177
; IF-EVL-INLOOP-NEXT: br i1 true, label [[FOR_COND_CLEANUP_LOOPEXIT:%.*]], label [[SCALAR_PH]]
178178
; IF-EVL-INLOOP: scalar.ph:
179179
; IF-EVL-INLOOP-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[FOR_BODY_PREHEADER]] ]
180-
; IF-EVL-INLOOP-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP12]], [[MIDDLE_BLOCK]] ], [ 0, [[FOR_BODY_PREHEADER]] ]
180+
; IF-EVL-INLOOP-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP11]], [[MIDDLE_BLOCK]] ], [ 0, [[FOR_BODY_PREHEADER]] ]
181181
; IF-EVL-INLOOP-NEXT: br label [[FOR_BODY:%.*]]
182182
; IF-EVL-INLOOP: for.body:
183183
; IF-EVL-INLOOP-NEXT: [[I_08:%.*]] = phi i32 [ [[INC:%.*]], [[FOR_BODY]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ]
184184
; IF-EVL-INLOOP-NEXT: [[R_07:%.*]] = phi i32 [ [[ADD:%.*]], [[FOR_BODY]] ], [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ]
185185
; IF-EVL-INLOOP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[X]], i32 [[I_08]]
186-
; IF-EVL-INLOOP-NEXT: [[TMP14:%.*]] = load i16, ptr [[ARRAYIDX]], align 2
187-
; IF-EVL-INLOOP-NEXT: [[CONV:%.*]] = sext i16 [[TMP14]] to i32
186+
; IF-EVL-INLOOP-NEXT: [[TMP13:%.*]] = load i16, ptr [[ARRAYIDX]], align 2
187+
; IF-EVL-INLOOP-NEXT: [[CONV:%.*]] = sext i16 [[TMP13]] to i32
188188
; IF-EVL-INLOOP-NEXT: [[ADD]] = add nsw i32 [[R_07]], [[CONV]]
189189
; IF-EVL-INLOOP-NEXT: [[INC]] = add nuw nsw i32 [[I_08]], 1
190190
; IF-EVL-INLOOP-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INC]], [[N]]
191191
; IF-EVL-INLOOP-NEXT: br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP_LOOPEXIT]], label [[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
192192
; IF-EVL-INLOOP: for.cond.cleanup.loopexit:
193-
; IF-EVL-INLOOP-NEXT: [[ADD_LCSSA:%.*]] = phi i32 [ [[ADD]], [[FOR_BODY]] ], [ [[TMP12]], [[MIDDLE_BLOCK]] ]
193+
; IF-EVL-INLOOP-NEXT: [[ADD_LCSSA:%.*]] = phi i32 [ [[ADD]], [[FOR_BODY]] ], [ [[TMP11]], [[MIDDLE_BLOCK]] ]
194194
; IF-EVL-INLOOP-NEXT: br label [[FOR_COND_CLEANUP]]
195195
; IF-EVL-INLOOP: for.cond.cleanup:
196196
; IF-EVL-INLOOP-NEXT: [[R_0_LCSSA:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[ADD_LCSSA]], [[FOR_COND_CLEANUP_LOOPEXIT]] ]

0 commit comments

Comments
 (0)