@@ -17,7 +17,7 @@ fde4_fre_offset_sizes:
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# CHECK: FuncDescEntry [0] {
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# CHECK: Start FRE Offset: 0
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# CHECK: FRE Type: Addr1 (0x0)
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- .cfi_startproc
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+ .cfi_startproc
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# CHECK: Frame Row Entry {
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# CHECK-NEXT: Start Address: 0x0
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# CHECK-NEXT: Return Address Signed: No
@@ -27,80 +27,80 @@ fde4_fre_offset_sizes:
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# CHECK-NEXT: RA Offset: -8
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.long 0
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# Uninteresting register no new fre, no effect on cfa
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- .cfi_offset 0 , 8
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+ .cfi_offset 0 , 8
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.long 0
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- .cfi_def_cfa_offset 0x78
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+ .cfi_def_cfa_offset 0x78
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# CHECK: Frame Row Entry {
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# CHECK-NEXT: Start Address: 0x8
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# CHECK-NEXT: Return Address Signed: No
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# CHECK-NEXT: Offset Size: B1 (0x0)
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# CHECK-NEXT: Base Register: SP (0x1)
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# CHECK-NEXT: CFA Offset: 120
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# CHECK-NEXT: RA Offset: -8
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- .long 0
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+ .long 0
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# Uninteresting register no new fre, no effect on cfa
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.cfi_rel_offset 1 , 8
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.long 0
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- .cfi_def_cfa_offset 0x80
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+ .cfi_def_cfa_offset 0x80
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# CHECK: Frame Row Entry {
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# CHECK-NEXT: Start Address: 0x10
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# CHECK-NEXT: Return Address Signed: No
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# CHECK-NEXT: Offset Size: B2 (0x1)
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# CHECK-NEXT: Base Register: SP (0x1)
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# CHECK-NEXT: CFA Offset: 128
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# CHECK-NEXT: RA Offset: -8
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- .long 0
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+ .long 0
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# Uninteresting register no new fre, no effect on cfa
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.cfi_val_offset 1 , 8
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.long 0
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- .cfi_def_cfa_offset 0x7FFF
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+ .cfi_def_cfa_offset 0x7FFF
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# CHECK: Frame Row Entry {
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# CHECK-NEXT: Start Address: 0x18
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# CHECK-NEXT: Return Address Signed: No
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# CHECK-NEXT: Offset Size: B2 (0x1)
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# CHECK-NEXT: Base Register: SP (0x1)
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# CHECK-NEXT: CFA Offset: 32767
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# CHECK-NEXT: RA Offset: -8
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- .long 0
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- .cfi_def_cfa_offset 0x8000
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+ .long 0
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+ .cfi_def_cfa_offset 0x8000
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# CHECK: Frame Row Entry {
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# CHECK-NEXT: Start Address: 0x1C
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# CHECK-NEXT: Return Address Signed: No
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# CHECK-NEXT: Offset Size: B4 (0x2)
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# CHECK-NEXT: Base Register: SP (0x1)
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# CHECK-NEXT: CFA Offset: 32768
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# CHECK-NEXT: RA Offset: -8
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- .long 0
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- .cfi_def_cfa_offset 0x8
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+ .long 0
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+ .cfi_def_cfa_offset 0x8
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# CHECK: Frame Row Entry {
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# CHECK-NEXT: Start Address: 0x20
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# CHECK-NEXT: Return Address Signed: No
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# CHECK-NEXT: Offset Size: B1 (0x0)
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# CHECK-NEXT: Base Register: SP (0x1)
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# CHECK-NEXT: CFA Offset: 8
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# CHECK-NEXT: RA Offset: -8
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- .long 0
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- .cfi_adjust_cfa_offset 0x8
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+ .long 0
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+ .cfi_adjust_cfa_offset 0x8
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# CHECK: Frame Row Entry {
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# CHECK-NEXT: Start Address: 0x24
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# CHECK-NEXT: Return Address Signed: No
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# CHECK-NEXT: Offset Size: B1 (0x0)
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# CHECK-NEXT: Base Register: SP (0x1)
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# CHECK-NEXT: CFA Offset: 16
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# CHECK-NEXT: RA Offset: -8
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- .long 0
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- .cfi_def_cfa_register 6 # switch to fp
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+ .long 0
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+ .cfi_def_cfa_register 6 # switch to fp
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# CHECK: Frame Row Entry {
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# CHECK-NEXT: Start Address: 0x28
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# CHECK-NEXT: Return Address Signed: No
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# CHECK-NEXT: Offset Size: B1 (0x0)
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# CHECK-NEXT: Base Register: FP (0x0)
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# CHECK-NEXT: CFA Offset: 16
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# CHECK-NEXT: RA Offset: -8
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- .long 0
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- .cfi_offset 7 , 32
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- # sp not the cfa but with large offset still changes encoding.
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- .cfi_offset 6 , 0x7FF8
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+ .long 0
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+ .cfi_offset 7 , 32
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+ # sp not the cfa but with large offset still changes encoding.
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+ .cfi_offset 6 , 0x7FF8
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# CHECK: Frame Row Entry {
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# CHECK-NEXT: Start Address: 0x2C
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# CHECK-NEXT: Return Address Signed: No
@@ -109,5 +109,75 @@ fde4_fre_offset_sizes:
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# CHECK-NEXT: CFA Offset: 16
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# CHECK-NEXT: RA Offset: -8
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# CHECK-NEXT: FP Offset: 32760
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- .long 0
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+ .long 0
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+ .cfi_endproc
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+
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+ .align 1024
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+ restore_reg:
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+ # CHECK: FuncDescEntry [1] {
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+ # CHECK: Start FRE Offset: 0x23
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+ # CHECK-NEXT: Num FREs: 3
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+ .cfi_startproc
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+ # CHECK: Frame Row Entry {
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+ # CHECK-NEXT: Start Address: 0x400
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+ # CHECK-NOT FP Offset{{.*}}
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+ # CHECK: }
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+ .long 0
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+ .cfi_offset 6 , 32
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+ # CHECK Frame Row Entry {
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+ # CHECK-NEXT Start Address: 0x404
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+ # CHECK: FP Offset: 32
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+ .long 0
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+ .cfi_restore 6
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+ # CHECK: Frame Row Entry {
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+ # CHECK-NEXT: Start Address: 0x408
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+ # CHECK-NOT FP Offset{{.*}}
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+ # CHECK: }
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+ .long 0
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+ .cfi_endproc
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+
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+ .align 1024
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+ remember_restore_state:
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+ # CHECK: FuncDescEntry [2] {
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+ # CHECK: Start FRE Offset: 0x2D
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+ # CHECK-NEXT: Num FREs: 4
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+ .cfi_startproc
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+ # CHECK: Frame Row Entry {
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+ # CHECK-NEXT: Start Address: 0x800
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+ # CHECK-NOT FP Offset{{.*}}
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+ # CHECK: }
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+ .long 0
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+ .cfi_offset 6 , 8
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+ .cfi_offset 7 , 16
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+ .cfi_offset 8 , 24
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+ # CHECK: Frame Row Entry {
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+ # CHECK-NEXT: Start Address: 0x804
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+ # CHECK: Base Register: SP (0x1)
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+ # CHECK-NEXT: CFA Offset: 8
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+ # CHECK-NEXT: RA Offset: -8
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+ # CHECK-NEXT: FP Offset: 8
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+ # CHECK-NEXT: }
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+ .long 0
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+ .cfi_remember_state
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+ # CHECK: Frame Row Entry {
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+ # CHECK-NEXT: Start Address: 0x808
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+ # CHECK: Base Register: SP (0x1)
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+ # CHECK-NEXT: CFA Offset: 8
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+ # CHECK-NEXT: RA Offset: -8
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+ # CHECK-NEXT: FP Offset: 32
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+ # CHECK-NEXT: }
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+ .cfi_offset 6 , 32
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+ .cfi_offset 7 , 40
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+ .cfi_offset 8 , 48
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+ .long 0
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+ # CHECK: Frame Row Entry {
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+ # CHECK-NEXT: Start Address: 0x80C
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+ # CHECK: Base Register: SP (0x1)
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+ # CHECK-NEXT: CFA Offset: 8
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+ # CHECK-NEXT: RA Offset: -8
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+ # CHECK-NEXT: FP Offset: 8
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+ # CHECK-NEXT: }
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+ .cfi_restore_state
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+ .long 0
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+
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.cfi_endproc
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