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sunshaocesunshaoce
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only add tests
1 parent 9b25edd commit 74e65af

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2 files changed

+180
-22
lines changed

2 files changed

+180
-22
lines changed

‎llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp‎

Lines changed: 0 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1049,19 +1049,6 @@ void RISCVInstructionSelector::preISelLower(MachineInstr &MI,
10491049
MRI->setType(DstReg, sXLen);
10501050
break;
10511051
}
1052-
case TargetOpcode::G_STORE: {
1053-
Register SrcReg = MI.getOperand(0).getReg();
1054-
MachineInstr *Def = MRI->getVRegDef(SrcReg);
1055-
if (Def && Def->getOpcode() == TargetOpcode::G_FCONSTANT) {
1056-
if (Def->getOperand(1).getFPImm()->getValueAPF().isPosZero()) {
1057-
MI.getOperand(0).setReg(RISCV::X0);
1058-
1059-
if (MRI->use_nodbg_empty(SrcReg))
1060-
Def->eraseFromParent();
1061-
}
1062-
}
1063-
break;
1064-
}
10651052
}
10661053
}
10671054

‎llvm/test/CodeGen/RISCV/GlobalISel/store-fp-zero-to-x0.ll‎

Lines changed: 180 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1,30 +1,66 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 -global-isel -mattr=+f -verify-machineinstrs < %s \
2+
; RUN: llc -global-isel -mtriple=riscv32 -global-isel -mattr=+f,+zfh < %s \
33
; RUN: | FileCheck %s --check-prefix=RV32
4-
; RUN: llc -mtriple=riscv64 -global-isel -mattr=+d -verify-machineinstrs < %s \
4+
; RUN: llc -global-isel -mtriple=riscv64 -global-isel -mattr=+d,+zfh < %s \
55
; RUN: | FileCheck %s --check-prefix=RV64
66

7+
define void @zero_f16(ptr %i) {
8+
; RV32-LABEL: zero_f16:
9+
; RV32: # %bb.0: # %entry
10+
; RV32-NEXT: fmv.h.x fa5, zero
11+
; RV32-NEXT: fsh fa5, 0(a0)
12+
; RV32-NEXT: ret
13+
;
14+
; RV64-LABEL: zero_f16:
15+
; RV64: # %bb.0: # %entry
16+
; RV64-NEXT: fmv.h.x fa5, zero
17+
; RV64-NEXT: fsh fa5, 0(a0)
18+
; RV64-NEXT: ret
19+
entry:
20+
store half 0.0, ptr %i, align 4
21+
ret void
22+
}
23+
24+
define void @zero_bf16(ptr %i) {
25+
; RV32-LABEL: zero_bf16:
26+
; RV32: # %bb.0: # %entry
27+
; RV32-NEXT: fmv.h.x fa5, zero
28+
; RV32-NEXT: fsh fa5, 0(a0)
29+
; RV32-NEXT: ret
30+
;
31+
; RV64-LABEL: zero_bf16:
32+
; RV64: # %bb.0: # %entry
33+
; RV64-NEXT: fmv.h.x fa5, zero
34+
; RV64-NEXT: fsh fa5, 0(a0)
35+
; RV64-NEXT: ret
36+
entry:
37+
store bfloat 0.0, ptr %i, align 4
38+
ret void
39+
}
40+
741
define void @zero_f32(ptr %i) {
842
; RV32-LABEL: zero_f32:
943
; RV32: # %bb.0: # %entry
10-
; RV32-NEXT: sw zero, 0(a0)
44+
; RV32-NEXT: fmv.w.x fa5, zero
45+
; RV32-NEXT: fsw fa5, 0(a0)
1146
; RV32-NEXT: ret
1247
;
1348
; RV64-LABEL: zero_f32:
1449
; RV64: # %bb.0: # %entry
15-
; RV64-NEXT: sw zero, 0(a0)
50+
; RV64-NEXT: fmv.w.x fa5, zero
51+
; RV64-NEXT: fsw fa5, 0(a0)
1652
; RV64-NEXT: ret
1753
entry:
18-
store float 0.000000e+00, ptr %i, align 4
54+
store float 0.0, ptr %i, align 4
1955
ret void
2056
}
2157

2258

2359
define void @zero_f64(ptr %i) {
2460
; RV32-LABEL: zero_f64:
2561
; RV32: # %bb.0: # %entry
26-
; RV32-NEXT: lui a1, %hi(.LCPI1_0)
27-
; RV32-NEXT: addi a1, a1, %lo(.LCPI1_0)
62+
; RV32-NEXT: lui a1, %hi(.LCPI3_0)
63+
; RV32-NEXT: addi a1, a1, %lo(.LCPI3_0)
2864
; RV32-NEXT: lw a2, 0(a1)
2965
; RV32-NEXT: lw a1, 4(a1)
3066
; RV32-NEXT: sw a2, 0(a0)
@@ -33,9 +69,144 @@ define void @zero_f64(ptr %i) {
3369
;
3470
; RV64-LABEL: zero_f64:
3571
; RV64: # %bb.0: # %entry
36-
; RV64-NEXT: sd zero, 0(a0)
72+
; RV64-NEXT: fmv.d.x fa5, zero
73+
; RV64-NEXT: fsd fa5, 0(a0)
74+
; RV64-NEXT: ret
75+
entry:
76+
store double 0.0, ptr %i, align 8
77+
ret void
78+
}
79+
80+
define void @zero_v1f32(ptr %i) {
81+
; RV32-LABEL: zero_v1f32:
82+
; RV32: # %bb.0: # %entry
83+
; RV32-NEXT: fmv.w.x fa5, zero
84+
; RV32-NEXT: fsw fa5, 0(a0)
85+
; RV32-NEXT: ret
86+
;
87+
; RV64-LABEL: zero_v1f32:
88+
; RV64: # %bb.0: # %entry
89+
; RV64-NEXT: fmv.w.x fa5, zero
90+
; RV64-NEXT: fsw fa5, 0(a0)
91+
; RV64-NEXT: ret
92+
entry:
93+
store <1 x float> <float 0.0>, ptr %i, align 8
94+
ret void
95+
}
96+
97+
define void @zero_v2f32(ptr %i) {
98+
; RV32-LABEL: zero_v2f32:
99+
; RV32: # %bb.0: # %entry
100+
; RV32-NEXT: fmv.w.x fa5, zero
101+
; RV32-NEXT: fsw fa5, 0(a0)
102+
; RV32-NEXT: fsw fa5, 4(a0)
103+
; RV32-NEXT: ret
104+
;
105+
; RV64-LABEL: zero_v2f32:
106+
; RV64: # %bb.0: # %entry
107+
; RV64-NEXT: fmv.w.x fa5, zero
108+
; RV64-NEXT: fsw fa5, 0(a0)
109+
; RV64-NEXT: fsw fa5, 4(a0)
110+
; RV64-NEXT: ret
111+
entry:
112+
store <2 x float> <float 0.0, float 0.0>, ptr %i, align 8
113+
ret void
114+
}
115+
116+
define void @zero_v4f32(ptr %i) {
117+
; RV32-LABEL: zero_v4f32:
118+
; RV32: # %bb.0: # %entry
119+
; RV32-NEXT: fmv.w.x fa5, zero
120+
; RV32-NEXT: fsw fa5, 0(a0)
121+
; RV32-NEXT: fsw fa5, 4(a0)
122+
; RV32-NEXT: fsw fa5, 8(a0)
123+
; RV32-NEXT: fsw fa5, 12(a0)
124+
; RV32-NEXT: ret
125+
;
126+
; RV64-LABEL: zero_v4f32:
127+
; RV64: # %bb.0: # %entry
128+
; RV64-NEXT: fmv.w.x fa5, zero
129+
; RV64-NEXT: fsw fa5, 0(a0)
130+
; RV64-NEXT: fsw fa5, 4(a0)
131+
; RV64-NEXT: fsw fa5, 8(a0)
132+
; RV64-NEXT: fsw fa5, 12(a0)
133+
; RV64-NEXT: ret
134+
entry:
135+
store <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>, ptr %i, align 8
136+
ret void
137+
}
138+
139+
define void @zero_v1f64(ptr %i) {
140+
; RV32-LABEL: zero_v1f64:
141+
; RV32: # %bb.0: # %entry
142+
; RV32-NEXT: lui a1, %hi(.LCPI7_0)
143+
; RV32-NEXT: addi a1, a1, %lo(.LCPI7_0)
144+
; RV32-NEXT: lw a2, 0(a1)
145+
; RV32-NEXT: lw a1, 4(a1)
146+
; RV32-NEXT: sw a2, 0(a0)
147+
; RV32-NEXT: sw a1, 4(a0)
148+
; RV32-NEXT: ret
149+
;
150+
; RV64-LABEL: zero_v1f64:
151+
; RV64: # %bb.0: # %entry
152+
; RV64-NEXT: fmv.d.x fa5, zero
153+
; RV64-NEXT: fsd fa5, 0(a0)
154+
; RV64-NEXT: ret
155+
entry:
156+
store <1 x double> <double 0.0>, ptr %i, align 8
157+
ret void
158+
}
159+
160+
define void @zero_v2f64(ptr %i) {
161+
; RV32-LABEL: zero_v2f64:
162+
; RV32: # %bb.0: # %entry
163+
; RV32-NEXT: lui a1, %hi(.LCPI8_0)
164+
; RV32-NEXT: addi a1, a1, %lo(.LCPI8_0)
165+
; RV32-NEXT: lw a2, 0(a1)
166+
; RV32-NEXT: lw a1, 4(a1)
167+
; RV32-NEXT: sw a2, 0(a0)
168+
; RV32-NEXT: sw a1, 4(a0)
169+
; RV32-NEXT: sw a2, 8(a0)
170+
; RV32-NEXT: sw a1, 12(a0)
171+
; RV32-NEXT: ret
172+
;
173+
; RV64-LABEL: zero_v2f64:
174+
; RV64: # %bb.0: # %entry
175+
; RV64-NEXT: fmv.d.x fa5, zero
176+
; RV64-NEXT: fsd fa5, 0(a0)
177+
; RV64-NEXT: fsd fa5, 8(a0)
178+
; RV64-NEXT: ret
179+
entry:
180+
store <2 x double> <double 0.0, double 0.0>, ptr %i, align 8
181+
ret void
182+
}
183+
184+
define void @zero_v4f64(ptr %i) {
185+
; RV32-LABEL: zero_v4f64:
186+
; RV32: # %bb.0: # %entry
187+
; RV32-NEXT: lui a1, %hi(.LCPI9_0)
188+
; RV32-NEXT: addi a1, a1, %lo(.LCPI9_0)
189+
; RV32-NEXT: lw a2, 0(a1)
190+
; RV32-NEXT: lw a1, 4(a1)
191+
; RV32-NEXT: sw a2, 0(a0)
192+
; RV32-NEXT: sw a1, 4(a0)
193+
; RV32-NEXT: sw a2, 8(a0)
194+
; RV32-NEXT: sw a1, 12(a0)
195+
; RV32-NEXT: sw a2, 16(a0)
196+
; RV32-NEXT: sw a1, 20(a0)
197+
; RV32-NEXT: sw a2, 24(a0)
198+
; RV32-NEXT: sw a1, 28(a0)
199+
; RV32-NEXT: ret
200+
;
201+
; RV64-LABEL: zero_v4f64:
202+
; RV64: # %bb.0: # %entry
203+
; RV64-NEXT: fmv.d.x fa5, zero
204+
; RV64-NEXT: fsd fa5, 0(a0)
205+
; RV64-NEXT: fsd fa5, 8(a0)
206+
; RV64-NEXT: fsd fa5, 16(a0)
207+
; RV64-NEXT: fsd fa5, 24(a0)
37208
; RV64-NEXT: ret
38209
entry:
39-
store double 0.000000e+00, ptr %i, align 8
210+
store <4 x double> <double 0.0, double 0.0, double 0.0, double 0.0>, ptr %i, align 8
40211
ret void
41212
}

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