Skip to content

Commit 7503b13

Browse files
RuhungRuhung
committed
[RISCV] Add MC layer support for Andes XAndesVSIntH extension.
1 parent c69a70b commit 7503b13

File tree

11 files changed

+143
-2
lines changed

11 files changed

+143
-2
lines changed

‎clang/test/Driver/print-supported-extensions-riscv.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -165,6 +165,7 @@
165165
// CHECK-NEXT: xandesvbfhcvt 5.0 'XAndesVBFHCvt' (Andes Vector BFLOAT16 Conversion Extension)
166166
// CHECK-NEXT: xandesvdot 5.0 'XAndesVDot' (Andes Vector Dot Product Extension)
167167
// CHECK-NEXT: xandesvpackfph 5.0 'XAndesVPackFPH' (Andes Vector Packed FP16 Extension)
168+
// CHECK-NEXT: xandesvsinth 5.0 'XAndesVSIntH' (Andes Vector Small INT Handling Extension)
168169
// CHECK-NEXT: xandesvsintload 5.0 'XAndesVSIntLoad' (Andes Vector INT4 Load Extension)
169170
// CHECK-NEXT: xcvalu 1.0 'XCValu' (CORE-V ALU Operations)
170171
// CHECK-NEXT: xcvbi 1.0 'XCVbi' (CORE-V Immediate Branching)

‎clang/test/Preprocessor/riscv-target-features-andes.c‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,7 @@
66
// CHECK-NOT: __riscv_xandesperf {{.*$}}
77
// CHECK-NOT: __riscv_xandesbfhcvt {{.*$}}
88
// CHECK-NOT: __riscv_xandesvbfhcvt {{.*$}}
9+
// CHECK-NOT: __riscv_xandesvsinth {{.*$}}
910
// CHECK-NOT: __riscv_xandesvsintload {{.*$}}
1011
// CHECK-NOT: __riscv_xandesvpackfph {{.*$}}
1112
// CHECK-NOT: __riscv_xandesvdot {{.*$}}
@@ -34,6 +35,14 @@
3435
// RUN: -o - | FileCheck --check-prefix=CHECK-XANDESVBFHCVT %s
3536
// CHECK-XANDESVBFHCVT: __riscv_xandesvbfhcvt 5000000{{$}}
3637

38+
// RUN: %clang --target=riscv32 \
39+
// RUN: -march=rv32i_xandesvsinth -E -dM %s \
40+
// RUN: -o - | FileCheck --check-prefix=CHECK-XANDESVSINTH %s
41+
// RUN: %clang --target=riscv64 \
42+
// RUN: -march=rv64i_xandesvsinth -E -dM %s \
43+
// RUN: -o - | FileCheck --check-prefix=CHECK-XANDESVSINTH %s
44+
// CHECK-XANDESVSINTH: __riscv_xandesvsinth 5000000{{$}}
45+
3746
// RUN: %clang --target=riscv32 \
3847
// RUN: -march=rv32i_xandesvsintload -E -dM %s \
3948
// RUN: -o - | FileCheck --check-prefix=CHECK-XANDESVSINTLOAD %s

‎llvm/docs/RISCVUsage.rst‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -527,6 +527,9 @@ The current vendor extensions supported are:
527527
``XAndesVBFHCvt``
528528
LLVM implements `version 5.0.0 of the Andes Vector BFLOAT16 Conversion Extension specification <https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf>`__ by Andes Technology. All instructions are prefixed with `nds.` as described in the specification.
529529

530+
``XAndesVSINTH``
531+
LLVM implements `version 5.0.0 of the Andes Vector Small Int Handling Extension specification <https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf>`__ by Andes Technology. All instructions are prefixed with `nds.` as described in the specification.
532+
530533
``XAndesVSINTLoad``
531534
LLVM implements `version 5.0.0 of the Andes Vector INT4 Load Extension specification <https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf>`__ by Andes Technology. All instructions are prefixed with `nds.` as described in the specification.
532535

‎llvm/docs/ReleaseNotes.md‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -126,6 +126,7 @@ Changes to the RISC-V Backend
126126
* Add support for Zvfbfa (Additional BF16 vector compute support)
127127
* Adds experimental support for the 'Zibi` (Branch with Immediate) extension.
128128
* Add support for Zvfofp8min (OFP8 conversion extension)
129+
* Adds assembler support for the Andes `XAndesvsinth` (Andes Vector Small Int Handling Extension).
129130

130131
Changes to the WebAssembly Backend
131132
----------------------------------

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -676,8 +676,8 @@ static constexpr FeatureBitset XTHeadGroup = {
676676
RISCV::FeatureVendorXTHeadVdot};
677677

678678
static constexpr FeatureBitset XAndesGroup = {
679-
RISCV::FeatureVendorXAndesPerf, RISCV::FeatureVendorXAndesBFHCvt,
680-
RISCV::FeatureVendorXAndesVBFHCvt,
679+
RISCV::FeatureVendorXAndesPerf, RISCV::FeatureVendorXAndesBFHCvt,
680+
RISCV::FeatureVendorXAndesVBFHCvt, RISCV::FeatureVendorXAndesVSIntH,
681681
RISCV::FeatureVendorXAndesVSIntLoad, RISCV::FeatureVendorXAndesVPackFPH,
682682
RISCV::FeatureVendorXAndesVDot};
683683

‎llvm/lib/Target/RISCV/RISCVFeatures.td‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1648,6 +1648,14 @@ def HasVendorXAndesVBFHCvt
16481648
AssemblerPredicate<(all_of FeatureVendorXAndesVBFHCvt),
16491649
"'XAndesVBFHCvt' (Andes Vector BFLOAT16 Conversion Extension)">;
16501650

1651+
def FeatureVendorXAndesVSIntH
1652+
: RISCVExtension<5, 0, "Andes Vector Small INT Handling Extension",
1653+
[FeatureStdExtZve32x]>;
1654+
def HasVendorXAndesVSIntH
1655+
: Predicate<"Subtarget->hasVendorXAndesVSIntH()">,
1656+
AssemblerPredicate<(all_of FeatureVendorXAndesVSIntH),
1657+
"'XAndesVSIntH' (Andes Vector Small INT Handling Extension)">;
1658+
16511659
def FeatureVendorXAndesVSIntLoad
16521660
: RISCVExtension<5, 0, "Andes Vector INT4 Load Extension",
16531661
[FeatureStdExtZve32x]>;

‎llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td‎

Lines changed: 53 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -362,6 +362,47 @@ class NDSRVInstSDGP<bits<3> funct3, string opcodestr>
362362
let mayStore = 1;
363363
}
364364

365+
class NDSRVInstVSINTLN<bits<5> funct5, string opcodestr>
366+
: RVInst<(outs VR:$vd), (ins GPRMemZeroOffset:$rs1),
367+
opcodestr, "$vd, ${rs1}", [], InstFormatR>,
368+
VLESchedMC {
369+
bits<5> rs1;
370+
bits<5> vd;
371+
372+
let Inst{31-26} = 0b000001;
373+
let Inst{25} = 1;
374+
let Inst{24-20} = funct5;
375+
let Inst{19-15} = rs1;
376+
let Inst{14-12} = 0b100;
377+
let Inst{11-7} = vd;
378+
let Inst{6-0} = OPC_CUSTOM_2.Value;
379+
let hasSideEffects = 0;
380+
let mayLoad = 1;
381+
let mayStore = 0;
382+
let Uses = [VTYPE, VL];
383+
}
384+
385+
class NDSRVInstVSINTCvt<bits<5> fucnt5, string opcodestr>
386+
: RVInst<(outs VR:$vd), (ins VR:$vs, VMaskOp:$vm),
387+
opcodestr, "$vd, $vs$vm", [], InstFormatR> {
388+
bits<5> vs;
389+
bits<5> vd;
390+
bit vm;
391+
392+
let Inst{31-26} = 0b000000;
393+
let Inst{25} = vm;
394+
let Inst{24-20} = vs;
395+
let Inst{19-15} = fucnt5;
396+
let Inst{14-12} = 0b100;
397+
let Inst{11-7} = vd;
398+
let Inst{6-0} = OPC_CUSTOM_2.Value;
399+
let hasSideEffects = 0;
400+
let mayLoad = 0;
401+
let mayStore = 0;
402+
let Uses = [FRM, VL, VTYPE];
403+
let RVVConstraint = VMConstraint;
404+
}
405+
365406
class NDSRVInstBFHCvt<bits<7> funct7, bits<5> rs1val, DAGOperand rdty,
366407
DAGOperand rs2ty, string opcodestr>
367408
: RVInstR<funct7, 0b100, OPC_CUSTOM_2, (outs rdty:$rd),
@@ -679,6 +720,18 @@ let Uses = [FRM, VL, VTYPE] in
679720
def NDS_VFNCVT_BF16_S : NDSRVInstVBFHCvt<0b00001, "nds.vfncvt.bf16.s">;
680721
}
681722

723+
//===----------------------------------------------------------------------===//
724+
// XAndesVSIntH
725+
//===----------------------------------------------------------------------===//
726+
727+
let Predicates = [HasVendorXAndesVSIntH] in {
728+
def NDS_VFWCVT_F_N : NDSRVInstVSINTCvt<0b00100, "nds.vfwcvt.f.n.v">;
729+
def NDS_VFWCVT_F_NU : NDSRVInstVSINTCvt<0b00101, "nds.vfwcvt.f.nu.v">;
730+
def NDS_VFWCVT_F_B : NDSRVInstVSINTCvt<0b00110, "nds.vfwcvt.f.b.v">;
731+
def NDS_VFWCVT_F_BU : NDSRVInstVSINTCvt<0b00111, "nds.vfwcvt.f.bu.v">;
732+
def NDS_VLE4_V : NDSRVInstVSINTLN<0b00000, "nds.vle4.v">;
733+
}
734+
682735
//===----------------------------------------------------------------------===//
683736
// XAndesVSIntLoad
684737
//===----------------------------------------------------------------------===//

‎llvm/test/CodeGen/RISCV/attributes-andes.ll‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,27 +3,31 @@
33
; RUN: llc -mtriple=riscv32 -mattr=+xandesperf %s -o - | FileCheck --check-prefix=RV32XANDESPERF %s
44
; RUN: llc -mtriple=riscv32 -mattr=+xandesbfhcvt %s -o - | FileCheck --check-prefix=RV32XANDESBFHCVT %s
55
; RUN: llc -mtriple=riscv32 -mattr=+xandesvbfhcvt %s -o - | FileCheck --check-prefix=RV32XANDESVBFHCVT %s
6+
; RUN: llc -mtriple=riscv32 -mattr=+xandesvsinth %s -o - | FileCheck --check-prefix=RV32XANDESVSINTH %s
67
; RUN: llc -mtriple=riscv32 -mattr=+xandesvsintload %s -o - | FileCheck --check-prefix=RV32XANDESVSINTLOAD %s
78
; RUN: llc -mtriple=riscv32 -mattr=+xandesvdot %s -o - | FileCheck --check-prefix=RV32XANDESVDOT %s
89
; RUN: llc -mtriple=riscv32 -mattr=+xandesvpackfph %s -o - | FileCheck --check-prefix=RV32XANDESVPACKFPH %s
910

1011
; RUN: llc -mtriple=riscv64 -mattr=+xandesperf %s -o - | FileCheck --check-prefix=RV64XANDESPERF %s
1112
; RUN: llc -mtriple=riscv64 -mattr=+xandesbfhcvt %s -o - | FileCheck --check-prefix=RV64XANDESBFHCVT %s
1213
; RUN: llc -mtriple=riscv64 -mattr=+xandesvbfhcvt %s -o - | FileCheck --check-prefix=RV64XANDESVBFHCVT %s
14+
; RUN: llc -mtriple=riscv64 -mattr=+xandesvsinth %s -o - | FileCheck --check-prefix=RV64XANDESVSINTH %s
1315
; RUN: llc -mtriple=riscv64 -mattr=+xandesvsintload %s -o - | FileCheck --check-prefix=RV64XANDESVSINTLOAD %s
1416
; RUN: llc -mtriple=riscv64 -mattr=+xandesvdot %s -o - | FileCheck --check-prefix=RV64XANDESVDOT %s
1517
; RUN: llc -mtriple=riscv64 -mattr=+xandesvpackfph %s -o - | FileCheck --check-prefix=RV64XANDESVPACKFPH %s
1618

1719
; RV32XANDESPERF: .attribute 5, "rv32i2p1_xandesperf5p0"
1820
; RV32XANDESBFHCVT: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_xandesbfhcvt5p0"
1921
; RV32XANDESVBFHCVT: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvl32b1p0_xandesvbfhcvt5p0"
22+
; RV32XANDESVSINTH: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xandesvsinth5p0"
2023
; RV32XANDESVSINTLOAD: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xandesvsintload5p0"
2124
; RV32XANDESVDOT: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xandesvdot5p0"
2225
; RV32XANDESVPACKFPH: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_xandesvpackfph5p0"
2326

2427
; RV64XANDESPERF: .attribute 5, "rv64i2p1_xandesperf5p0"
2528
; RV64XANDESBFHCVT: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_xandesbfhcvt5p0"
2629
; RV64XANDESVBFHCVT: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvl32b1p0_xandesvbfhcvt5p0"
30+
; RV64XANDESVSINTH: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xandesvsinth5p0"
2731
; RV64XANDESVSINTLOAD: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xandesvsintload5p0"
2832
; RV64XANDESVDOT: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xandesvdot5p0"
2933
; RV64XANDESVPACKFPH: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_xandesvpackfph5p0"

‎llvm/test/CodeGen/RISCV/features-info.ll‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -191,6 +191,7 @@
191191
; CHECK-NEXT: xandesvbfhcvt - 'XAndesVBFHCvt' (Andes Vector BFLOAT16 Conversion Extension).
192192
; CHECK-NEXT: xandesvdot - 'XAndesVDot' (Andes Vector Dot Product Extension).
193193
; CHECK-NEXT: xandesvpackfph - 'XAndesVPackFPH' (Andes Vector Packed FP16 Extension).
194+
; CHECK-NEXT: xandesvsinth - 'XAndesVSIntH' (Andes Vector Small INT Handling Extension).
194195
; CHECK-NEXT: xandesvsintload - 'XAndesVSIntLoad' (Andes Vector INT4 Load Extension).
195196
; CHECK-NEXT: xcvalu - 'XCValu' (CORE-V ALU Operations).
196197
; CHECK-NEXT: xcvbi - 'XCVbi' (CORE-V Immediate Branching).

‎llvm/test/MC/RISCV/xandesvsinth-valid.s‎

Lines changed: 60 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,60 @@
1+
# XAndesVSIntLoad - Andes Vector INT4 Load Extension
2+
# RUN: llvm-mc %s -triple=riscv32 -mattr=+xandesvsinth -show-encoding \
3+
# RUN: | FileCheck -check-prefixes=CHECK-ASM %s
4+
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xandesvsinth < %s \
5+
# RUN: | llvm-objdump --mattr=+xandesvsinth -M no-aliases -d -r - \
6+
# RUN: | FileCheck -check-prefixes=CHECK-OBJ %s
7+
# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
8+
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
9+
# RUN: llvm-mc %s -triple=riscv64 -mattr=+xandesvsinth -show-encoding \
10+
# RUN: | FileCheck -check-prefixes=CHECK-ASM %s
11+
# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+xandesvsinth < %s \
12+
# RUN: | llvm-objdump --mattr=+xandesvsinth -M no-aliases -d -r - \
13+
# RUN: | FileCheck -check-prefixes=CHECK-OBJ %s
14+
# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
15+
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
16+
# CHECK-OBJ: nds.vfwcvt.f.n.v v8, v10
17+
# CHECK-ASM: nds.vfwcvt.f.n.v v8, v10
18+
# CHECK-ASM: encoding: [0x5b,0x44,0xa2,0x02]
19+
# CHECK-ERROR: instruction requires the following: 'XAndesVSIntH' (Andes Vector Small INT Handling Extension){{$}}
20+
nds.vfwcvt.f.n.v v8, v10
21+
# CHECK-OBJ: nds.vfwcvt.f.n.v v8, v10, v0.t
22+
# CHECK-ASM: nds.vfwcvt.f.n.v v8, v10, v0.t
23+
# CHECK-ASM: encoding: [0x5b,0x44,0xa2,0x00]
24+
# CHECK-ERROR: instruction requires the following: 'XAndesVSIntH' (Andes Vector Small INT Handling Extension){{$}}
25+
nds.vfwcvt.f.n.v v8, v10, v0.t
26+
# CHECK-OBJ: nds.vfwcvt.f.nu.v v8, v10
27+
# CHECK-ASM: nds.vfwcvt.f.nu.v v8, v10
28+
# CHECK-ASM: encoding: [0x5b,0xc4,0xa2,0x02]
29+
# CHECK-ERROR: instruction requires the following: 'XAndesVSIntH' (Andes Vector Small INT Handling Extension){{$}}
30+
nds.vfwcvt.f.nu.v v8, v10
31+
# CHECK-OBJ: nds.vfwcvt.f.nu.v v8, v10, v0.t
32+
# CHECK-ASM: nds.vfwcvt.f.nu.v v8, v10, v0.t
33+
# CHECK-ASM: encoding: [0x5b,0xc4,0xa2,0x00]
34+
# CHECK-ERROR: instruction requires the following: 'XAndesVSIntH' (Andes Vector Small INT Handling Extension){{$}}
35+
nds.vfwcvt.f.nu.v v8, v10, v0.t
36+
# CHECK-OBJ: nds.vfwcvt.f.b.v v8, v10
37+
# CHECK-ASM: nds.vfwcvt.f.b.v v8, v10
38+
# CHECK-ASM: encoding: [0x5b,0x44,0xa3,0x02]
39+
# CHECK-ERROR: instruction requires the following: 'XAndesVSIntH' (Andes Vector Small INT Handling Extension){{$}}
40+
nds.vfwcvt.f.b.v v8, v10
41+
# CHECK-OBJ: nds.vfwcvt.f.b.v v8, v10, v0.t
42+
# CHECK-ASM: nds.vfwcvt.f.b.v v8, v10, v0.t
43+
# CHECK-ASM: encoding: [0x5b,0x44,0xa3,0x00]
44+
# CHECK-ERROR: instruction requires the following: 'XAndesVSIntH' (Andes Vector Small INT Handling Extension){{$}}
45+
nds.vfwcvt.f.b.v v8, v10, v0.t
46+
# CHECK-OBJ: nds.vfwcvt.f.bu.v v8, v10
47+
# CHECK-ASM: nds.vfwcvt.f.bu.v v8, v10
48+
# CHECK-ASM: encoding: [0x5b,0xc4,0xa3,0x02]
49+
# CHECK-ERROR: instruction requires the following: 'XAndesVSIntH' (Andes Vector Small INT Handling Extension){{$}}
50+
nds.vfwcvt.f.bu.v v8, v10
51+
# CHECK-OBJ: nds.vfwcvt.f.bu.v v8, v10, v0.t
52+
# CHECK-ASM: nds.vfwcvt.f.bu.v v8, v10, v0.t
53+
# CHECK-ASM: encoding: [0x5b,0xc4,0xa3,0x00]
54+
# CHECK-ERROR: instruction requires the following: 'XAndesVSIntH' (Andes Vector Small INT Handling Extension){{$}}
55+
nds.vfwcvt.f.bu.v v8, v10, v0.t
56+
# CHECK-OBJ: nds.vle4.v v8, (a0)
57+
# CHECK-ASM: nds.vle4.v v8, (a0)
58+
# CHECK-ASM: encoding: [0x5b,0x44,0x05,0x06]
59+
# CHECK-ERROR: instruction requires the following: 'XAndesVSIntH' (Andes Vector Small INT Handling Extension){{$}}
60+
nds.vle4.v v8, (a0)

0 commit comments

Comments
 (0)