Skip to content

Commit 75099c2

Browse files
authored
[ConstantFolding] Fold scalable get_active_lane_masks (#156659)
Scalable get_active_lane_mask intrinsics with a range of 0 can be lowered to zeroinitializer. This helps remove no-op scalable masked stores and loads.
1 parent 0f13cae commit 75099c2

File tree

2 files changed

+40
-0
lines changed

2 files changed

+40
-0
lines changed

llvm/lib/Analysis/ConstantFolding.cpp

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4252,6 +4252,13 @@ static Constant *ConstantFoldScalableVectorCall(
42524252

42534253
return ConstantInt::getFalse(SVTy);
42544254
}
4255+
case Intrinsic::get_active_lane_mask: {
4256+
auto Op0 = cast<ConstantInt>(Operands[0])->getValue();
4257+
auto Op1 = cast<ConstantInt>(Operands[1])->getValue();
4258+
if (Op0.uge(Op1))
4259+
return ConstantVector::getNullValue(SVTy);
4260+
break;
4261+
}
42554262
default:
42564263
break;
42574264
}

llvm/test/Transforms/InstSimplify/ConstProp/active-lane-mask.ll

Lines changed: 33 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -307,6 +307,39 @@ entry:
307307
ret <4 x float> %var33
308308
}
309309

310+
define <vscale x 4 x i1> @nxv4i1_12_12() {
311+
; CHECK-LABEL: @nxv4i1_12_12(
312+
; CHECK-NEXT: entry:
313+
; CHECK-NEXT: ret <vscale x 4 x i1> zeroinitializer
314+
;
315+
entry:
316+
%mask = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i32(i32 12, i32 12)
317+
ret <vscale x 4 x i1> %mask
318+
}
319+
320+
define <vscale x 4 x i1> @nxv4i1_8_4() {
321+
; CHECK-LABEL: @nxv4i1_8_4(
322+
; CHECK-NEXT: entry:
323+
; CHECK-NEXT: ret <vscale x 4 x i1> zeroinitializer
324+
;
325+
entry:
326+
%mask = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i32(i32 8, i32 4)
327+
ret <vscale x 4 x i1> %mask
328+
}
329+
330+
define <vscale x 16 x i1> @nxv16i1_0_0() {
331+
; CHECK-LABEL: @nxv16i1_0_0(
332+
; CHECK-NEXT: entry:
333+
; CHECK-NEXT: ret <vscale x 16 x i1> zeroinitializer
334+
;
335+
entry:
336+
%mask = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 0, i64 0)
337+
ret <vscale x 16 x i1> %mask
338+
}
339+
310340
declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32)
311341
declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32, i32)
312342
declare <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32, i32)
343+
344+
declare <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i32(i32, i32)
345+
declare <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64, i64)

0 commit comments

Comments
 (0)