[RISCV] Implement computeKnownBitsForTargetNode for SHL_ADD

Author: pfusik

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -21568,6 +21568,15 @@ void RISCVTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
     Known = Known.sext(BitWidth);
     break;
   }
+  case RISCVISD::SHL_ADD: {
+    KnownBits Known2;
+    Known = DAG.computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
+    Known2 = DAG.computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
+    Known = KnownBits::shl(Known, Known2);
+    Known2 = DAG.computeKnownBits(Op.getOperand(2), DemandedElts, Depth + 1);
+    Known = KnownBits::add(Known, Known2);
+    break;
+  }
   case RISCVISD::CTZW: {
     KnownBits Known2 = DAG.computeKnownBits(Op.getOperand(0), Depth + 1);
     unsigned PossibleTZ = Known2.trunc(32).countMaxTrailingZeros();

llvm/test/CodeGen/RISCV/rv32zba.ll

@@ -1283,16 +1283,15 @@ define ptr @shl_add_knownbits(ptr %p, i32 %i) {
 ; RV32ZBA-NEXT:    slli a1, a1, 18
 ; RV32ZBA-NEXT:    srli a1, a1, 18
 ; RV32ZBA-NEXT:    sh1add a1, a1, a1
-; RV32ZBA-NEXT:    slli a1, a1, 1
-; RV32ZBA-NEXT:    srli a1, a1, 3
+; RV32ZBA-NEXT:    srli a1, a1, 2
 ; RV32ZBA-NEXT:    add a0, a0, a1
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV32XANDESPERF-LABEL: shl_add_knownbits:
 ; RV32XANDESPERF:       # %bb.0:
 ; RV32XANDESPERF-NEXT:    nds.bfoz a1, a1, 13, 0
 ; RV32XANDESPERF-NEXT:    nds.lea.h a1, a1, a1
-; RV32XANDESPERF-NEXT:    nds.bfoz a1, a1, 30, 2
+; RV32XANDESPERF-NEXT:    srli a1, a1, 2
 ; RV32XANDESPERF-NEXT:    add a0, a0, a1
 ; RV32XANDESPERF-NEXT:    ret
   %and = and i32 %i, 16383

llvm/test/CodeGen/RISCV/rv64zba.ll

@@ -4654,16 +4654,15 @@ define ptr @shl_add_knownbits(ptr %p, i64 %i) {
 ; RV64ZBA-NEXT:    slli a1, a1, 50
 ; RV64ZBA-NEXT:    srli a1, a1, 50
 ; RV64ZBA-NEXT:    sh1add a1, a1, a1
-; RV64ZBA-NEXT:    slli a1, a1, 1
-; RV64ZBA-NEXT:    srli a1, a1, 3
+; RV64ZBA-NEXT:    srli a1, a1, 2
 ; RV64ZBA-NEXT:    add a0, a0, a1
 ; RV64ZBA-NEXT:    ret
 ;
 ; RV64XANDESPERF-LABEL: shl_add_knownbits:
 ; RV64XANDESPERF:       # %bb.0:
 ; RV64XANDESPERF-NEXT:    nds.bfoz a1, a1, 13, 0
 ; RV64XANDESPERF-NEXT:    nds.lea.h a1, a1, a1
-; RV64XANDESPERF-NEXT:    nds.bfoz a1, a1, 62, 2
+; RV64XANDESPERF-NEXT:    srli a1, a1, 2
 ; RV64XANDESPERF-NEXT:    add a0, a0, a1
 ; RV64XANDESPERF-NEXT:    ret
   %and = and i64 %i, 16383