@@ -687,22 +687,22 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI,
687687 case RISCVVector::BI__builtin_rvv_vaeskf2_vi_tu:
688688 case RISCVVector::BI__builtin_rvv_vaeskf2_vi:
689689 case RISCVVector::BI__builtin_rvv_vsm4k_vi_tu: {
690- QualType Op1Type = TheCall->getArg (0 )->getType ();
691- QualType Op2Type = TheCall->getArg (1 )->getType ();
692- return CheckInvalidVLENandLMUL (TI, TheCall, SemaRef, Op1Type , 128 ) ||
693- CheckInvalidVLENandLMUL (TI, TheCall, SemaRef, Op2Type , 128 ) ||
690+ QualType Arg0Type = TheCall->getArg (0 )->getType ();
691+ QualType Arg1Type = TheCall->getArg (1 )->getType ();
692+ return CheckInvalidVLENandLMUL (TI, TheCall, SemaRef, Arg0Type , 128 ) ||
693+ CheckInvalidVLENandLMUL (TI, TheCall, SemaRef, Arg1Type , 128 ) ||
694694 SemaRef.BuiltinConstantArgRange (TheCall, 2 , 0 , 31 );
695695 }
696696 case RISCVVector::BI__builtin_rvv_vsm3c_vi_tu:
697697 case RISCVVector::BI__builtin_rvv_vsm3c_vi: {
698- QualType Op1Type = TheCall->getArg (0 )->getType ();
699- return CheckInvalidVLENandLMUL (TI, TheCall, SemaRef, Op1Type , 256 ) ||
698+ QualType Arg0Type = TheCall->getArg (0 )->getType ();
699+ return CheckInvalidVLENandLMUL (TI, TheCall, SemaRef, Arg0Type , 256 ) ||
700700 SemaRef.BuiltinConstantArgRange (TheCall, 2 , 0 , 31 );
701701 }
702702 case RISCVVector::BI__builtin_rvv_vaeskf1_vi:
703703 case RISCVVector::BI__builtin_rvv_vsm4k_vi: {
704- QualType Op1Type = TheCall->getArg (0 )->getType ();
705- return CheckInvalidVLENandLMUL (TI, TheCall, SemaRef, Op1Type , 128 ) ||
704+ QualType Arg0Type = TheCall->getArg (0 )->getType ();
705+ return CheckInvalidVLENandLMUL (TI, TheCall, SemaRef, Arg0Type , 128 ) ||
706706 SemaRef.BuiltinConstantArgRange (TheCall, 1 , 0 , 31 );
707707 }
708708 case RISCVVector::BI__builtin_rvv_vaesdf_vv:
@@ -727,33 +727,34 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI,
727727 case RISCVVector::BI__builtin_rvv_vaesz_vs_tu:
728728 case RISCVVector::BI__builtin_rvv_vsm4r_vv_tu:
729729 case RISCVVector::BI__builtin_rvv_vsm4r_vs_tu: {
730- QualType Op1Type = TheCall->getArg (0 )->getType ();
731- QualType Op2Type = TheCall->getArg (1 )->getType ();
732- return CheckInvalidVLENandLMUL (TI, TheCall, SemaRef, Op1Type , 128 ) ||
733- CheckInvalidVLENandLMUL (TI, TheCall, SemaRef, Op2Type , 128 );
730+ QualType Arg0Type = TheCall->getArg (0 )->getType ();
731+ QualType Arg1Type = TheCall->getArg (1 )->getType ();
732+ return CheckInvalidVLENandLMUL (TI, TheCall, SemaRef, Arg0Type , 128 ) ||
733+ CheckInvalidVLENandLMUL (TI, TheCall, SemaRef, Arg1Type , 128 );
734734 }
735735 case RISCVVector::BI__builtin_rvv_vsha2ch_vv:
736736 case RISCVVector::BI__builtin_rvv_vsha2cl_vv:
737737 case RISCVVector::BI__builtin_rvv_vsha2ms_vv:
738738 case RISCVVector::BI__builtin_rvv_vsha2ch_vv_tu:
739739 case RISCVVector::BI__builtin_rvv_vsha2cl_vv_tu:
740740 case RISCVVector::BI__builtin_rvv_vsha2ms_vv_tu: {
741- QualType Op1Type = TheCall->getArg (0 )->getType ();
742- QualType Op2Type = TheCall->getArg (1 )->getType ();
743- QualType Op3Type = TheCall->getArg (2 )->getType ();
741+ QualType Arg0Type = TheCall->getArg (0 )->getType ();
742+ QualType Arg1Type = TheCall->getArg (1 )->getType ();
743+ QualType Arg2Type = TheCall->getArg (2 )->getType ();
744744 ASTContext::BuiltinVectorTypeInfo Info =
745- Context.getBuiltinVectorTypeInfo (Op1Type ->castAs <BuiltinType>());
745+ Context.getBuiltinVectorTypeInfo (Arg0Type ->castAs <BuiltinType>());
746746 uint64_t ElemSize = Context.getTypeSize (Info.ElementType );
747747 if (ElemSize == 64 && !TI.hasFeature (" zvknhb" ))
748748 return Diag (TheCall->getBeginLoc (),
749749 diag::err_riscv_builtin_requires_extension)
750750 << /* IsExtension */ true << TheCall->getSourceRange () << " zvknhb" ;
751751
752- return CheckInvalidVLENandLMUL (TI, TheCall, SemaRef, Op1Type ,
752+ return CheckInvalidVLENandLMUL (TI, TheCall, SemaRef, Arg0Type ,
753753 ElemSize * 4 ) ||
754- CheckInvalidVLENandLMUL (TI, TheCall, SemaRef, Op2Type ,
754+ CheckInvalidVLENandLMUL (TI, TheCall, SemaRef, Arg1Type ,
755755 ElemSize * 4 ) ||
756- CheckInvalidVLENandLMUL (TI, TheCall, SemaRef, Op3Type, ElemSize * 4 );
756+ CheckInvalidVLENandLMUL (TI, TheCall, SemaRef, Arg2Type,
757+ ElemSize * 4 );
757758 }
758759
759760 case RISCVVector::BI__builtin_rvv_sf_vc_i_se:
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