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YuriPlyakhinMrSidims
YuriPlyakhin
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MrSidims
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[SPIR-V] Add SPV_INTEL_2d_block_io extension (#140140)
Adds additional subgroup block prefetch, load, load transposed, load transformed and store instructions to read two-dimensional blocks of data from a two-dimensional region of memory, or to write two-dimensional blocks of data to a two-dimensional region of memory. Spec: https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extensions/INTEL/SPV_INTEL_2d_block_io.asciidoc --------- Co-authored-by: Dmitry Sidorov <[email protected]>
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‎llvm/docs/SPIRVUsage.rst‎

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@@ -153,6 +153,8 @@ list of supported SPIR-V extensions, sorted alphabetically by their extension na
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- Adds atomic add instruction on floating-point numbers.
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* - ``SPV_EXT_shader_atomic_float_min_max``
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- Adds atomic min and max instruction on floating-point numbers.
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* - ``SPV_INTEL_2d_block_io``
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- Adds additional subgroup block prefetch, load, load transposed, load transformed and store instructions to read two-dimensional blocks of data from a two-dimensional region of memory, or to write two-dimensional blocks of data to a two dimensional region of memory.
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* - ``SPV_INTEL_arbitrary_precision_integers``
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- Allows generating arbitrary width integer types.
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* - ``SPV_INTEL_bindless_images``

‎llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp‎

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@@ -1076,6 +1076,24 @@ static bool buildTernaryBitwiseFunctionINTELInst(
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return true;
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}
10781078

1079+
/// Helper function for building Intel's 2d block io instructions.
1080+
static bool build2DBlockIOINTELInst(const SPIRV::IncomingCall *Call,
1081+
unsigned Opcode,
1082+
MachineIRBuilder &MIRBuilder,
1083+
SPIRVGlobalRegistry *GR) {
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// Generate SPIRV instruction accordingly.
1085+
if (Call->isSpirvOp())
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return buildOpFromWrapper(MIRBuilder, Opcode, Call, Register(0));
1087+
1088+
auto MIB = MIRBuilder.buildInstr(Opcode)
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.addDef(Call->ReturnRegister)
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.addUse(GR->getSPIRVTypeID(Call->ReturnType));
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for (unsigned i = 0; i < Call->Arguments.size(); ++i)
1092+
MIB.addUse(Call->Arguments[i]);
1093+
1094+
return true;
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}
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static unsigned getNumComponentsForDim(SPIRV::Dim::Dim dim) {
10801098
switch (dim) {
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case SPIRV::Dim::DIM_1D:
@@ -2319,6 +2337,17 @@ generateTernaryBitwiseFunctionINTELInst(const SPIRV::IncomingCall *Call,
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return buildTernaryBitwiseFunctionINTELInst(Call, Opcode, MIRBuilder, GR);
23202338
}
23212339

2340+
static bool generate2DBlockIOINTELInst(const SPIRV::IncomingCall *Call,
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MachineIRBuilder &MIRBuilder,
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SPIRVGlobalRegistry *GR) {
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// Lookup the instruction opcode in the TableGen records.
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const SPIRV::DemangledBuiltin *Builtin = Call->Builtin;
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unsigned Opcode =
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SPIRV::lookupNativeBuiltin(Builtin->Name, Builtin->Set)->Opcode;
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return build2DBlockIOINTELInst(Call, Opcode, MIRBuilder, GR);
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}
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static bool buildNDRange(const SPIRV::IncomingCall *Call,
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MachineIRBuilder &MIRBuilder,
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SPIRVGlobalRegistry *GR) {
@@ -2902,6 +2931,8 @@ std::optional<bool> lowerBuiltin(const StringRef DemangledCall,
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return generateBindlessImageINTELInst(Call.get(), MIRBuilder, GR);
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case SPIRV::TernaryBitwiseINTEL:
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return generateTernaryBitwiseFunctionINTELInst(Call.get(), MIRBuilder, GR);
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case SPIRV::Block2DLoadStore:
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return generate2DBlockIOINTELInst(Call.get(), MIRBuilder, GR);
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}
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return false;
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}

‎llvm/lib/Target/SPIRV/SPIRVBuiltins.td‎

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@@ -68,6 +68,7 @@ def ICarryBorrow : BuiltinGroup;
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def ExtendedBitOps : BuiltinGroup;
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def BindlessINTEL : BuiltinGroup;
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def TernaryBitwiseINTEL : BuiltinGroup;
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def Block2DLoadStore : BuiltinGroup;
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//===----------------------------------------------------------------------===//
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// Class defining a demangled builtin record. The information in the record
@@ -718,6 +719,13 @@ defm : DemangledNativeBuiltin<"__spirv_ConvertHandleToSampledImageINTEL", OpenCL
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// SPV_INTEL_ternary_bitwise_function builtin records:
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defm : DemangledNativeBuiltin<"__spirv_BitwiseFunctionINTEL", OpenCL_std, TernaryBitwiseINTEL, 4, 4, OpBitwiseFunctionINTEL>;
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722+
// SPV_INTEL_2d_block_io builtin records
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defm : DemangledNativeBuiltin<"__spirv_Subgroup2DBlockLoadINTEL", OpenCL_std, Block2DLoadStore, 10, 10, OpSubgroup2DBlockLoadINTEL>;
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defm : DemangledNativeBuiltin<"__spirv_Subgroup2DBlockLoadTransposeINTEL", OpenCL_std, Block2DLoadStore, 10, 10, OpSubgroup2DBlockLoadTransposeINTEL>;
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defm : DemangledNativeBuiltin<"__spirv_Subgroup2DBlockLoadTransformINTEL", OpenCL_std, Block2DLoadStore, 10, 10, OpSubgroup2DBlockLoadTransformINTEL>;
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defm : DemangledNativeBuiltin<"__spirv_Subgroup2DBlockPrefetchINTEL", OpenCL_std, Block2DLoadStore, 9, 9, OpSubgroup2DBlockPrefetchINTEL>;
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defm : DemangledNativeBuiltin<"__spirv_Subgroup2DBlockStoreINTEL", OpenCL_std, Block2DLoadStore, 10, 10, OpSubgroup2DBlockStoreINTEL>;
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//===----------------------------------------------------------------------===//
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// Class defining a work/sub group builtin that should be translated into a
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// SPIR-V instruction using the defined properties.

‎llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp‎

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@@ -97,7 +97,9 @@ static const std::map<std::string, SPIRV::Extension::Extension, std::less<>>
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SPIRV::Extension::Extension::
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SPV_INTEL_subgroup_matrix_multiply_accumulate},
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{"SPV_INTEL_ternary_bitwise_function",
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SPIRV::Extension::Extension::SPV_INTEL_ternary_bitwise_function}};
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SPIRV::Extension::Extension::SPV_INTEL_ternary_bitwise_function},
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{"SPV_INTEL_2d_block_io",
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SPIRV::Extension::Extension::SPV_INTEL_2d_block_io}};
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bool SPIRVExtensionsParser::parse(cl::Option &O, StringRef ArgName,
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StringRef ArgValue,

‎llvm/lib/Target/SPIRV/SPIRVInstrInfo.td‎

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@@ -936,3 +936,20 @@ def OpAliasScopeListDeclINTEL: Op<5913, (outs ID:$res), (ins variable_ops),
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// SPV_INTEL_ternary_bitwise_function
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def OpBitwiseFunctionINTEL: Op<6242, (outs ID:$res), (ins TYPE:$type, ID:$a, ID:$b, ID:$c, ID:$lut_index),
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"$res = OpBitwiseFunctionINTEL $type $a $b $c $lut_index">;
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// SPV_INTEL_2d_block_io
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def OpSubgroup2DBlockLoadINTEL: Op<6231, (outs), (ins ID:$element_size, ID:$block_width, ID:$block_height,
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ID:$block_count, ID:$src_base_ptr, ID:$memory_width, ID:$memory_height, ID:$memory_pitch, ID:$coord, ID:$dst_ptr),
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"OpSubgroup2DBlockLoadINTEL $element_size $block_width $block_height $block_count $src_base_ptr $memory_width $memory_height $memory_pitch $coord $dst_ptr">;
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def OpSubgroup2DBlockLoadTransposeINTEL: Op<6233, (outs), (ins ID:$element_size, ID:$block_width, ID:$block_height,
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ID:$block_count, ID:$src_base_ptr, ID:$memory_width, ID:$memory_height, ID:$memory_pitch, ID:$coord, ID:$dst_ptr),
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"OpSubgroup2DBlockLoadTransposeINTEL $element_size $block_width $block_height $block_count $src_base_ptr $memory_width $memory_height $memory_pitch $coord $dst_ptr">;
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def OpSubgroup2DBlockLoadTransformINTEL: Op<6232, (outs), (ins ID:$element_size, ID:$block_width, ID:$block_height,
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ID:$block_count, ID:$src_base_ptr, ID:$memory_width, ID:$memory_height, ID:$memory_pitch, ID:$coord, ID:$dst_ptr),
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"OpSubgroup2DBlockLoadTransformINTEL $element_size $block_width $block_height $block_count $src_base_ptr $memory_width $memory_height $memory_pitch $coord $dst_ptr">;
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def OpSubgroup2DBlockPrefetchINTEL: Op<6234, (outs), (ins ID:$element_size, ID:$block_width, ID:$block_height,
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ID:$block_count, ID:$src_base_ptr, ID:$memory_width, ID:$memory_height, ID:$memory_pitch, ID:$coord),
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"OpSubgroup2DBlockPrefetchINTEL $element_size $block_width $block_height $block_count $src_base_ptr $memory_width $memory_height $memory_pitch $coord">;
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def OpSubgroup2DBlockStoreINTEL: Op<6235, (outs), (ins ID:$element_size, ID:$block_width, ID:$block_height,
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ID:$block_count, ID:$src_ptr, ID:$dst_base_ptr, ID:$memory_width, ID:$memory_height, ID:$memory_pitch, ID:$coord),
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"OpSubgroup2DBlockStoreINTEL $element_size $block_width $block_height $block_count $src_ptr $dst_base_ptr $memory_width $memory_height $memory_pitch $coord">;

‎llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp‎

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@@ -1739,6 +1739,30 @@ void addInstrRequirements(const MachineInstr &MI,
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Reqs.addExtension(SPIRV::Extension::SPV_INTEL_bindless_images);
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Reqs.addCapability(SPIRV::Capability::BindlessImagesINTEL);
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break;
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case SPIRV::OpSubgroup2DBlockLoadINTEL:
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case SPIRV::OpSubgroup2DBlockLoadTransposeINTEL:
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case SPIRV::OpSubgroup2DBlockLoadTransformINTEL:
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case SPIRV::OpSubgroup2DBlockPrefetchINTEL:
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case SPIRV::OpSubgroup2DBlockStoreINTEL: {
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if (!ST.canUseExtension(SPIRV::Extension::SPV_INTEL_2d_block_io))
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report_fatal_error("OpSubgroup2DBlock[Load/LoadTranspose/LoadTransform/"
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"Prefetch/Store]INTEL instructions require the "
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"following SPIR-V extension: SPV_INTEL_2d_block_io",
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false);
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Reqs.addExtension(SPIRV::Extension::SPV_INTEL_2d_block_io);
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Reqs.addCapability(SPIRV::Capability::Subgroup2DBlockIOINTEL);
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const auto OpCode = MI.getOpcode();
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if (OpCode == SPIRV::OpSubgroup2DBlockLoadTransposeINTEL) {
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Reqs.addCapability(SPIRV::Capability::Subgroup2DBlockTransposeINTEL);
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break;
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}
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if (OpCode == SPIRV::OpSubgroup2DBlockLoadTransformINTEL) {
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Reqs.addCapability(SPIRV::Capability::Subgroup2DBlockTransformINTEL);
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break;
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}
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break;
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}
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case SPIRV::OpKill: {
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Reqs.addCapability(SPIRV::Capability::Shader);
17441768
} break;

‎llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td‎

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@@ -315,6 +315,7 @@ defm SPV_INTEL_memory_access_aliasing : ExtensionOperand<118>;
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defm SPV_INTEL_fp_max_error : ExtensionOperand<119>;
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defm SPV_INTEL_ternary_bitwise_function : ExtensionOperand<120>;
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defm SPV_INTEL_subgroup_matrix_multiply_accumulate : ExtensionOperand<121>;
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defm SPV_INTEL_2d_block_io : ExtensionOperand<122>;
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319320
//===----------------------------------------------------------------------===//
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// Multiclass used to define Capabilities enum values and at the same time
@@ -517,6 +518,9 @@ defm MemoryAccessAliasingINTEL : CapabilityOperand<5910, 0, 0, [SPV_INTEL_memory
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defm FPMaxErrorINTEL : CapabilityOperand<6169, 0, 0, [SPV_INTEL_fp_max_error], []>;
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defm TernaryBitwiseFunctionINTEL : CapabilityOperand<6241, 0, 0, [SPV_INTEL_ternary_bitwise_function], []>;
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defm SubgroupMatrixMultiplyAccumulateINTEL : CapabilityOperand<6236, 0, 0, [SPV_INTEL_subgroup_matrix_multiply_accumulate], []>;
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defm Subgroup2DBlockIOINTEL : CapabilityOperand<6228, 0, 0, [SPV_INTEL_2d_block_io], []>;
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defm Subgroup2DBlockTransformINTEL : CapabilityOperand<6229, 0, 0, [SPV_INTEL_2d_block_io], [Subgroup2DBlockIOINTEL]>;
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defm Subgroup2DBlockTransposeINTEL : CapabilityOperand<6230, 0, 0, [SPV_INTEL_2d_block_io], [Subgroup2DBlockIOINTEL]>;
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521525
//===----------------------------------------------------------------------===//
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// Multiclass used to define SourceLanguage enum values and at the same time

‎llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_2d_block_io/2d_block_io_generic.ll‎

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@@ -0,0 +1,48 @@
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; RUN: not llc -O0 -mtriple=spirv64-unknown-unknown %s -o %t.spvt 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
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; RUN: llc -O0 -verify-machineinstrs -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_2d_block_io %s -o - | FileCheck %s
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; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s --spirv-ext=+SPV_INTEL_2d_block_io -o - -filetype=obj | spirv-val %}
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; CHECK-ERROR: LLVM ERROR: OpSubgroup2DBlock[Load/LoadTranspose/LoadTransform/Prefetch/Store]INTEL
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; CHECK-ERROR-SAME: instructions require the following SPIR-V extension: SPV_INTEL_2d_block_io
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8+
; CHECK: OpCapability Subgroup2DBlockIOINTEL
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; CHECK: OpCapability Subgroup2DBlockTransformINTEL
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; CHECK: OpCapability Subgroup2DBlockTransposeINTEL
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; CHECK: OpExtension "SPV_INTEL_2d_block_io"
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; CHECK-DAG: %[[Int8Ty:[0-9]+]] = OpTypeInt 8 0
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; CHECK-DAG: %[[Int32Ty:[0-9]+]] = OpTypeInt 32 0
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; CHECK-DAG: %[[Const42:[0-9]+]] = OpConstant %[[Int32Ty]] 42
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; CHECK-DAG: %[[VoidTy:[0-9]+]] = OpTypeVoid
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; CHECK-DAG: %[[GlbPtrTy:[0-9]+]] = OpTypePointer CrossWorkgroup %[[Int8Ty]]
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; CHECK-DAG: %[[VectorTy:[0-9]+]] = OpTypeVector %[[Int32Ty]] 2
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; CHECK-DAG: %[[PrvPtrTy:[0-9]+]] = OpTypePointer Function %[[Int8Ty]]
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; CHECK: %[[BaseSrc:[0-9]+]] = OpFunctionParameter %[[GlbPtrTy]]
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; CHECK: %[[BaseDst:[0-9]+]] = OpFunctionParameter %[[GlbPtrTy]]
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; CHECK: %[[Width:[0-9]+]] = OpFunctionParameter %[[Int32Ty]]
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; CHECK: %[[Height:[0-9]+]] = OpFunctionParameter %[[Int32Ty]]
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; CHECK: %[[Pitch:[0-9]+]] = OpFunctionParameter %[[Int32Ty]]
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; CHECK: %[[Coord:[0-9]+]] = OpFunctionParameter %[[VectorTy]]
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; CHECK: %[[Dst:[0-9]+]] = OpFunctionParameter %[[PrvPtrTy]]
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; CHECK: %[[Src:[0-9]+]] = OpFunctionParameter %[[PrvPtrTy]]
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; CHECK: OpSubgroup2DBlockLoadINTEL %[[Const42]] %[[Const42]] %[[Const42]] %[[Const42]] %[[BaseSrc]] %[[Width]] %[[Height]] %[[Pitch]] %[[Coord]] %[[Dst]]
29+
; CHECK: OpSubgroup2DBlockLoadTransformINTEL %[[Const42]] %[[Const42]] %[[Const42]] %[[Const42]] %[[BaseSrc]] %[[Width]] %[[Height]] %[[Pitch]] %[[Coord]] %[[Dst]]
30+
; CHECK: OpSubgroup2DBlockLoadTransposeINTEL %[[Const42]] %[[Const42]] %[[Const42]] %[[Const42]] %[[BaseSrc]] %[[Width]] %[[Height]] %[[Pitch]] %[[Coord]] %[[Dst]]
31+
; CHECK: OpSubgroup2DBlockPrefetchINTEL %[[Const42]] %[[Const42]] %[[Const42]] %[[Const42]] %[[BaseSrc]] %[[Width]] %[[Height]] %[[Pitch]] %[[Coord]]
32+
; CHECK: OpSubgroup2DBlockStoreINTEL %[[Const42]] %[[Const42]] %[[Const42]] %[[Const42]] %[[Src]] %[[BaseDst]] %[[Width]] %[[Height]] %[[Pitch]] %[[Coord]]
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34+
define spir_func void @foo(ptr addrspace(1) %base_address, ptr addrspace(1) %dst_base_pointer, i32 %width, i32 %height, i32 %pitch, <2 x i32> %coord, ptr %dst_pointer, ptr %src_pointer) {
35+
entry:
36+
call spir_func void @_Z32__spirv_Subgroup2DBlockLoadINTELiiiiPU3AS1KviiiDv2_iPv(i32 42, i32 42, i32 42, i32 42, ptr addrspace(1) %base_address, i32 %width, i32 %height, i32 %pitch, <2 x i32> %coord, ptr %dst_pointer)
37+
call spir_func void @_Z41__spirv_Subgroup2DBlockLoadTransformINTELiiiiPU3AS1KviiiDv2_iPv(i32 42, i32 42, i32 42, i32 42, ptr addrspace(1) %base_address, i32 %width, i32 %height, i32 %pitch, <2 x i32> %coord, ptr %dst_pointer)
38+
call spir_func void @_Z41__spirv_Subgroup2DBlockLoadTransposeINTELiiiiPU3AS1KviiiDv2_iPv(i32 42, i32 42, i32 42, i32 42, ptr addrspace(1) %base_address, i32 %width, i32 %height, i32 %pitch, <2 x i32> %coord, ptr %dst_pointer)
39+
call spir_func void @_Z36__spirv_Subgroup2DBlockPrefetchINTELiiiiPU3AS1KviiiDv2_i(i32 42, i32 42, i32 42, i32 42, ptr addrspace(1) %base_address, i32 %width, i32 %height, i32 %pitch, <2 x i32> %coord)
40+
call spir_func void @_Z33__spirv_Subgroup2DBlockStoreINTELiiiiPKvPU3AS1viiiDv2_i(i32 42, i32 42, i32 42, i32 42, ptr %src_pointer, ptr addrspace(1) %dst_base_pointer, i32 %width, i32 %height, i32 %pitch, <2 x i32> %coord)
41+
ret void
42+
}
43+
44+
declare spir_func void @_Z32__spirv_Subgroup2DBlockLoadINTELiiiiPU3AS1KviiiDv2_iPv(i32, i32, i32, i32, ptr addrspace(1), i32, i32, i32, <2 x i32>, ptr)
45+
declare spir_func void @_Z41__spirv_Subgroup2DBlockLoadTransformINTELiiiiPU3AS1KviiiDv2_iPv(i32, i32, i32, i32, ptr addrspace(1), i32, i32, i32, <2 x i32>, ptr)
46+
declare spir_func void @_Z41__spirv_Subgroup2DBlockLoadTransposeINTELiiiiPU3AS1KviiiDv2_iPv(i32, i32, i32, i32, ptr addrspace(1), i32, i32, i32, <2 x i32>, ptr)
47+
declare spir_func void @_Z36__spirv_Subgroup2DBlockPrefetchINTELiiiiPU3AS1KviiiDv2_i(i32, i32, i32, i32, ptr addrspace(1), i32, i32, i32, <2 x i32>)
48+
declare spir_func void @_Z33__spirv_Subgroup2DBlockStoreINTELiiiiPKvPU3AS1viiiDv2_i(i32, i32, i32, i32, ptr, ptr addrspace(1), i32, i32, i32, <2 x i32>)

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