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rastogishubhamrastogishubham
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[InstrRef] Preserve debug instr num in aarch64-ldst-opt.
The aarch64-ldst-opt pass tries to merge two load instructions (LDR*) to a load pair instruction (LDP*). When merging the instructions, there is a case where one of the loads would have to also be sign extended. In either case, (sign extend or not), the pass needs to preserve the debug-instr-number from the original loads to the load pair instruction to make sure debug info isn't loast in the case where instruction referencing is being used. This patch addresses that problem.
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‎llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp‎

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Original file line numberDiff line numberDiff line change
@@ -965,6 +965,40 @@ static void updateDefinedRegisters(MachineInstr &MI, LiveRegUnits &Units,
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Units.addReg(MOP.getReg());
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}
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/// Find the DBG_INSTR_REF instruction that references the \p InstrNum
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static std::optional<MachineInstr *> findDebugInstrRef(MachineBasicBlock *MBB,
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unsigned InstrNum) {
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for (auto &MI : *MBB) {
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if (MI.isDebugRef())
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if (MI.getOperand(2).getInstrRefInstrIndex() == InstrNum)
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return &MI;
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}
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return std::nullopt;
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}
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/// Set the correct debug-instr-number and the operand index in case of a merge.
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static void setDebugInstrNum(MachineBasicBlock::iterator OriginalInstr,
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MachineInstrBuilder &MIB, unsigned InstrNumToFind,
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unsigned InstrNumToSet, MachineBasicBlock *MBB) {
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auto InstrRefMI = findDebugInstrRef(MBB, InstrNumToFind);
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if (InstrRefMI) {
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auto *MI = *InstrRefMI;
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MI->getOperand(2).setInstrRefInstrIndex(InstrNumToSet);
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// Set the Instruction Reference Op Index to be the same as the operand of
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// the new merged pair instruction.
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auto Reg = OriginalInstr->getOperand(0).getReg();
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unsigned OperandNo = 0;
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for (auto Op : MIB->operands()) {
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if (Op.getReg() == Reg)
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break;
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OperandNo++;
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}
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MI->getOperand(2).setInstrRefOpIndex(OperandNo);
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}
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}
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MachineBasicBlock::iterator
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AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator Paired,
@@ -1227,6 +1261,30 @@ AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
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.addImm(0)
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.addImm(31);
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(void)MIBSXTW;
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if (I->peekDebugInstrNum()) {
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auto InstrNum = I->peekDebugInstrNum();
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// If I is the instruction which got sign extended, restore the debug
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// instruction number from I to the SBFMXri instruction
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if (DstRegX == I->getOperand(0).getReg())
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MIBSXTW->setDebugInstrNum(InstrNum);
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else {
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MIB->setDebugInstrNum(InstrNum);
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setDebugInstrNum(I, MIB, InstrNum, InstrNum, MBB);
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}
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}
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if (Paired->peekDebugInstrNum()) {
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auto InstrNum = Paired->peekDebugInstrNum();
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// If Paired is the instruction which got sign extended, restore the debug
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// instruction number from Paired to the SBFMXri instruction
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if (DstRegX == Paired->getOperand(0).getReg())
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MIBSXTW->setDebugInstrNum(InstrNum);
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else {
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MIB->setDebugInstrNum(InstrNum);
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setDebugInstrNum(Paired, MIB, InstrNum, InstrNum, MBB);
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}
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}
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LLVM_DEBUG(dbgs() << " Extend operand:\n ");
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LLVM_DEBUG(((MachineInstr *)MIBSXTW)->print(dbgs()));
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} else if (Opc == AArch64::LDR_ZXI || Opc == AArch64::STR_ZXI) {
@@ -1240,6 +1298,29 @@ AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
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MOp1.setReg(AArch64::Q0 + (MOp1.getReg() - AArch64::Z0));
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LLVM_DEBUG(((MachineInstr *)MIB)->print(dbgs()));
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} else {
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// Restore the debug instruction numbers to the merged instruction.
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bool UseNewDebugInstrNum = false;
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unsigned NewDebugInstrNum;
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if (I->peekDebugInstrNum() && Paired->peekDebugInstrNum()) {
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// Both instructions contain debug instruction numbers. We need to set a
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// new instruction number for the paired instruction and update the
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// DBG_INSTR_REFs that reference the instruction numbers of both
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// instructions and update them.
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NewDebugInstrNum = MIB->getDebugInstrNum();
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UseNewDebugInstrNum = true;
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}
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if (I->peekDebugInstrNum())
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setDebugInstrNum(
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I, MIB, I->peekDebugInstrNum(),
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UseNewDebugInstrNum ? NewDebugInstrNum : I->peekDebugInstrNum(), MBB);
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if (Paired->peekDebugInstrNum())
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setDebugInstrNum(Paired, MIB, Paired->peekDebugInstrNum(),
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UseNewDebugInstrNum ? NewDebugInstrNum
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: Paired->peekDebugInstrNum(),
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MBB);
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LLVM_DEBUG(((MachineInstr *)MIB)->print(dbgs()));
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}
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LLVM_DEBUG(dbgs() << "\n");

‎llvm/test/CodeGen/AArch64/aarch64-ldst-opt-instr-ref.mir‎

Lines changed: 79 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,79 @@
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# RUN: llc -mtriple=aarch64-unknown-linux-gnu -o - %s -run-pass=aarch64-ldst-opt | FileCheck %s
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# This testcase was obtained by looking at FileCheck.cpp and reducing it down via llvm-reduce
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# The aarch64-ldst-opt pass tries to merge load instructions from LDR* to a load pair or LDP* instruction, in such a case, we must ensure that the debug-instr-number is properly preserved for instruction referencing.
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# Check that in the case of a sign extend, the debug instruction number is transferred to the sign extend instruction (SBFMXri in this case), whereas the LDP instruction gets the other debug instruction number for the load that doesn't get sign extended.
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# CHECK: $w[[REG1:[0-9]+]], renamable $w[[REG2:[0-9]+]] = LDPWi renamable ${{[a-z0-9]+}}, 0, debug-instr-number [[DBG_INSTR_NUM1:[0-9]+]]
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# CHECK-NEXT: $w[[REG1]] = KILL $w[[REG1]], implicit-def $x[[REG1]]
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# CHECK-NEXT: $x[[REG1]] = SBFMXri $x[[REG1]], 0, 31, debug-instr-number [[DBG_INSTR_NUM2:[0-9]+]]
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# CHECK-NEXT: DBG_INSTR_REF ![[DBG1:[0-9]+]], !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_fragment, 64, 64), dbg-instr-ref([[DBG_INSTR_NUM1]], 1), debug-location ![[DBG2:[0-9]+]]
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# CHECK-NEXT: DBG_INSTR_REF ![[DBG1]], !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_fragment, 64, 32), dbg-instr-ref([[DBG_INSTR_NUM2]], 0), debug-location ![[DBG2]]
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# Check that in the case there is no sign extend, the LDP instruction gets a new debug instruction number and both the DBG_INSTR_REFs use the new instruction number.
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# CHECK: renamable $x[[REG3:[0-9]+]], renamable $x[[REG4:[0-9]+]] = LDPXi renamable ${{[a-z0-9]+}}, 0, debug-instr-number [[DBG_INSTR_NUM3:[0-9]+]]
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# CHECK-NEXT: DBG_INSTR_REF ![[DBG3:[0-9]+]], !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_fragment, 64, 64), dbg-instr-ref([[DBG_INSTR_NUM3]], 1), debug-location ![[DBG4:[0-9]+]]
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# CHECK-NEXT: DBG_INSTR_REF ![[DBG3]], !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_fragment, 64, 32), dbg-instr-ref([[DBG_INSTR_NUM3]], 0), debug-location ![[DBG4]]
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--- |
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define i64 @_ZNK4llvm9StringRef4sizeEv(ptr readonly captures(none) %this) local_unnamed_addr #0 {
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entry:
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%Length = getelementptr i8, ptr %this, i64 8
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%0 = load i64, ptr %Length, align 4
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ret i64 %0
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}
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define ptr @_ZNK4llvm9StringRef4dataEv(ptr readonly captures(none) %this) local_unnamed_addr #0 {
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entry:
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%0 = load ptr, ptr %this, align 8
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ret ptr %0
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}
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define void @_ZNK4llvm7Pattern5matchENS_9StringRefERKNS_9SourceMgrE(ptr readonly captures(none) %agg.result) local_unnamed_addr !dbg !3 {
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%call1541 = load volatile ptr, ptr null, align 4294967296, !dbg !9
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%FullMatch.sroa.1.0.agg.result.sroa_idx = getelementptr inbounds nuw i8, ptr %agg.result, i64 8
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ret void
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}
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define void @_ZNK4llvm7Pattern5matchENS_9StringRefERKNS_9SourceMgrE2(ptr readonly captures(none) %agg.result) local_unnamed_addr !dbg !10 {
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%call1541 = load volatile ptr, ptr null, align 4294967296, !dbg !11
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%FullMatch.sroa.1.0.agg.result.sroa_idx = getelementptr inbounds nuw i8, ptr %agg.result, i64 8
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ret void
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}
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!llvm.module.flags = !{!0}
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!llvm.dbg.cu = !{!1}
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!0 = !{i32 2, !"Debug Info Version", i32 3}
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!1 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !2, isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, sdk: "MacOSX15.3.sdk")
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!2 = !DIFile(filename: "/Users/shubhamrastogi/Development/llvm-project-instr-ref/llvm-project/llvm/lib/FileCheck/FileCheck.cpp", directory: "/Users/shubhamrastogi/Development/llvm-project-instr-ref/llvm-project/build-baseline-stage2", checksumkind: CSK_MD5, checksum: "ac1d2352ab68b965fe7993c780cf92d7")
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!3 = distinct !DISubprogram(scope: null, type: !4, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !6)
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!4 = distinct !DISubroutineType(types: !5)
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!5 = !{}
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!6 = !{!7}
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!7 = !DILocalVariable(name: "FullMatch", scope: !3, line: 1152, type: !8)
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!8 = distinct !DICompositeType(tag: DW_TAG_class_type, size: 128, identifier: "_ZTSN4llvm9StringRefE")
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!9 = !DILocation(line: 0, scope: !3)
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!10 = distinct !DISubprogram(scope: null, type: !4, spFlags: DISPFlagDefinition, unit: !1, retainedNodes: !12)
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!11 = !DILocation(line: 0, scope: !10)
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!12 = !{!13}
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!13 = !DILocalVariable(name: "FullMatch", scope: !10, line: 1152, type: !14)
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!14 = distinct !DICompositeType(tag: DW_TAG_class_type, size: 128, identifier: "_ZTSN4llvm9StringRefE")
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name: _ZNK4llvm9StringRef4sizeEv
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---
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name: _ZNK4llvm9StringRef4dataEv
64+
...
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name: _ZNK4llvm7Pattern5matchENS_9StringRefERKNS_9SourceMgrE
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body: |
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bb.0 (%ir-block.0):
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renamable $w1 = LDRWui renamable $x0, 1, debug-instr-number 1 :: (load (s64) from %ir.FullMatch.sroa.1.0.agg.result.sroa_idx, align 1)
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DBG_INSTR_REF !7, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_fragment, 64, 64), dbg-instr-ref(1, 0), debug-location !9
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renamable $x0 = LDRSWui killed renamable $x0, 0, debug-instr-number 2 :: (load (s64) from %ir.agg.result)
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DBG_INSTR_REF !7, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_fragment, 64, 32), dbg-instr-ref(2, 0), debug-location !9
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...
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name: _ZNK4llvm7Pattern5matchENS_9StringRefERKNS_9SourceMgrE2
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body: |
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bb.0 (%ir-block.0):
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renamable $x1 = LDRXui renamable $x0, 1, debug-instr-number 1 :: (load (s64) from %ir.FullMatch.sroa.1.0.agg.result.sroa_idx, align 1)
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DBG_INSTR_REF !13, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_fragment, 64, 64), dbg-instr-ref(1, 0), debug-location !11
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renamable $x0 = LDRXui killed renamable $x0, 0, debug-instr-number 2 :: (load (s64) from %ir.agg.result)
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DBG_INSTR_REF !13, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_fragment, 64, 32), dbg-instr-ref(2, 0), debug-location !11

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