fix fixme

Author: Thorsten Schütt

llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

@@ -393,7 +393,9 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
                                  {v8s16, p0, s128, 8},
                                  {v2s32, p0, s64, 8},
                                  {v4s32, p0, s128, 8},
-                                 {v2s64, p0, s128, 8}})
+                                 {v2s64, p0, s128, 8},
+                                 // SVE vscale x 64 bit base sizes
+                                 {nxv4s16, p0, nxv4s16, 8}})
       // These extends are also legal
       .legalForTypesWithMemDesc(
           {{s32, p0, s8, 8}, {s32, p0, s16, 8}, {s64, p0, s32, 8}})
@@ -1330,11 +1332,12 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
 
   getActionDefinitionsBuilder({G_SCMP, G_UCMP}).lower();
 
-  // FIXME: {nxv2s16, nxv4s16}
   getActionDefinitionsBuilder(G_EXTRACT_SUBVECTOR)
       .legalFor({{v8s8, v16s8}, {v4s16, v8s16}, {v2s32, v4s32}})
-      .legalFor(HasSVE,
-                {{nxv2s16, nxv8s16}, {nxv4s16, nxv8s16}, {nxv2s32, nxv4s32}})
+      .legalFor(HasSVE, {{nxv2s16, nxv4s16},
+                         {nxv2s16, nxv8s16},
+                         {nxv4s16, nxv8s16},
+                         {nxv2s32, nxv4s32}})
       .widenScalarOrEltToNextPow2(0)
       .immIdx(0); // Inform verifier imm idx 0 is handled.
 

llvm/test/CodeGen/AArch64/extract_subvector.ll

@@ -51,3 +51,18 @@ define void @extract_nxv2i16_nxv8i16(<vscale x 8 x i16> %arg, ptr %p) {
   store <vscale x 2 x i16> %ext, ptr %p
   ret void
 }
+
+define void @extract_nxv2i16_nxv4i16(ptr %p, ptr %p2) {
+; CHECK-LABEL: extract_nxv2i16_nxv4i16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.s
+; CHECK-NEXT:    ld1h { z0.s }, p0/z, [x0]
+; CHECK-NEXT:    ptrue p0.d
+; CHECK-NEXT:    uunpklo z0.d, z0.s
+; CHECK-NEXT:    st1h { z0.d }, p0, [x1]
+; CHECK-NEXT:    ret
+  %vector = load <vscale x 4 x i16>, ptr %p
+  %ext = call <vscale x 2 x i16> @llvm.vector.extract.nxv2i16.nxv4i16(<vscale x 4 x i16> %vector, i64 0)
+  store <vscale x 2 x i16> %ext, ptr %p2
+  ret void
+}