[GISel] Funnel shift combiner port from SelectionDAG ISel to GlobalISel

The funnel shift combiner rule from 4a3708c is currently missing from
GlobalISel. The following is a port of that combiner to GlobalISel.

Author: axelcool1234

llvm/test/CodeGen/AArch64/funnel-shift.ll

@@ -674,14 +674,12 @@ define i32 @or_shl_fshl_simplify(i32 %x, i32 %y, i32 %s) {
 ; CHECK-GI-LABEL: or_shl_fshl_simplify:
 ; CHECK-GI:       // %bb.0:
 ; CHECK-GI-NEXT:    mov w8, #31 // =0x1f
-; CHECK-GI-NEXT:    and w9, w2, #0x1f
-; CHECK-GI-NEXT:    lsr w10, w0, #1
-; CHECK-GI-NEXT:    lsl w11, w1, w2
+; CHECK-GI-NEXT:    lsr w9, w0, #1
+; CHECK-GI-NEXT:    and w10, w2, #0x1f
 ; CHECK-GI-NEXT:    bic w8, w8, w2
-; CHECK-GI-NEXT:    lsl w9, w1, w9
-; CHECK-GI-NEXT:    lsr w8, w10, w8
-; CHECK-GI-NEXT:    orr w9, w9, w11
-; CHECK-GI-NEXT:    orr w0, w9, w8
+; CHECK-GI-NEXT:    lsl w10, w1, w10
+; CHECK-GI-NEXT:    lsr w8, w9, w8
+; CHECK-GI-NEXT:    orr w0, w10, w8
 ; CHECK-GI-NEXT:    ret
   %shy = shl i32 %y, %s
   %fun = call i32 @llvm.fshl.i32(i32 %y, i32 %x, i32 %s)
@@ -702,14 +700,12 @@ define i32 @or_lshr_fshr_simplify(i32 %x, i32 %y, i32 %s) {
 ; CHECK-GI-LABEL: or_lshr_fshr_simplify:
 ; CHECK-GI:       // %bb.0:
 ; CHECK-GI-NEXT:    mov w8, #31 // =0x1f
-; CHECK-GI-NEXT:    and w9, w2, #0x1f
-; CHECK-GI-NEXT:    lsl w10, w0, #1
-; CHECK-GI-NEXT:    lsr w11, w1, w2
+; CHECK-GI-NEXT:    lsl w9, w0, #1
+; CHECK-GI-NEXT:    and w10, w2, #0x1f
 ; CHECK-GI-NEXT:    bic w8, w8, w2
-; CHECK-GI-NEXT:    lsr w9, w1, w9
-; CHECK-GI-NEXT:    lsl w8, w10, w8
-; CHECK-GI-NEXT:    orr w9, w11, w9
-; CHECK-GI-NEXT:    orr w0, w9, w8
+; CHECK-GI-NEXT:    lsl w8, w9, w8
+; CHECK-GI-NEXT:    lsr w9, w1, w10
+; CHECK-GI-NEXT:    orr w0, w8, w9
 ; CHECK-GI-NEXT:    ret
   %shy = lshr i32 %y, %s
   %fun = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 %s)

llvm/test/CodeGen/RISCV/GlobalISel/shift.ll

@@ -113,7 +113,6 @@ define i32 @test_fshl_i32(i32 %x, i32 %_, i32 %y) {
 ; RV32-NEXT:    sll a0, a0, a2
 ; RV32-NEXT:    srli a1, a1, 1
 ; RV32-NEXT:    srl a1, a1, a3
-; RV32-NEXT:    or a0, a0, a0
 ; RV32-NEXT:    or a0, a0, a1
 ; RV32-NEXT:    ret
 ;
@@ -123,7 +122,6 @@ define i32 @test_fshl_i32(i32 %x, i32 %_, i32 %y) {
 ; RV64-NEXT:    sllw a0, a0, a2
 ; RV64-NEXT:    srliw a1, a1, 1
 ; RV64-NEXT:    srlw a1, a1, a3
-; RV64-NEXT:    or a0, a0, a0
 ; RV64-NEXT:    or a0, a0, a1
 ; RV64-NEXT:    ret
   %fshl = call i32 @llvm.fshl.i32(i32 %x, i32 %_, i32 %y)
@@ -137,20 +135,18 @@ define i32 @test_fshr_i32(i32 %_, i32 %x, i32 %y) {
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    not a3, a2
 ; RV32-NEXT:    slli a0, a0, 1
-; RV32-NEXT:    srl a1, a1, a2
 ; RV32-NEXT:    sll a0, a0, a3
-; RV32-NEXT:    or a1, a1, a1
-; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    srl a1, a1, a2
+; RV32-NEXT:    or a0, a0, a1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: test_fshr_i32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    not a3, a2
 ; RV64-NEXT:    slli a0, a0, 1
-; RV64-NEXT:    srlw a1, a1, a2
 ; RV64-NEXT:    sllw a0, a0, a3
-; RV64-NEXT:    or a1, a1, a1
-; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    srlw a1, a1, a2
+; RV64-NEXT:    or a0, a0, a1
 ; RV64-NEXT:    ret
   %fshr = call i32 @llvm.fshr.i32(i32 %_, i32 %x, i32 %y)
   %lshr = lshr i32 %x, %y