[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6

[skip ci]

Author: vitalybuka

.github/new-prs-labeler.yml

@@ -722,7 +722,12 @@ mlgo:
   - llvm/include/llvm/Analysis/IR2Vec.h
   - llvm/lib/Analysis/IR2Vec.cpp
   - llvm/lib/Analysis/models/**
+  - llvm/include/llvm/CodeGen/MIR2Vec.h
+  - llvm/lib/CodeGen/MIR2Vec.cpp
   - llvm/test/Analysis/IR2Vec/**
+  - llvm/test/CodeGen/MIR2Vec/**
+  - llvm/unittests/Analysis/IR2VecTest.cpp
+  - llvm/unittests/CodeGen/MIR2VecTest.cpp
   - llvm/tools/llvm-ir2vec/**
   - llvm/docs/CommandGuide/llvm-ir2vec.rst
 

clang/test/Driver/print-supported-extensions-riscv.c

@@ -216,7 +216,7 @@
 // CHECK-NEXT:     zibi                 0.1       'Zibi' (Branch with Immediate)
 // CHECK-NEXT:     zicfilp              1.0       'Zicfilp' (Landing pad)
 // CHECK-NEXT:     zicfiss              1.0       'Zicfiss' (Shadow stack)
-// CHECK-NEXT:     zalasr               0.1       'Zalasr' (Load-Acquire and Store-Release Instructions)
+// CHECK-NEXT:     zalasr               0.9       'Zalasr' (Load-Acquire and Store-Release Instructions)
 // CHECK-NEXT:     zvbc32e              0.7       'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements)
 // CHECK-NEXT:     zvfbfa               0.1       'Zvfbfa' (Additional BF16 vector compute support)
 // CHECK-NEXT:     zvfofp8min           0.2       'Zvfofp8min' (Vector OFP8 Converts)

clang/test/Driver/riscv-arch.c

@@ -384,9 +384,9 @@
 // RUN: not %clang --target=riscv32-unknown-elf -march=rv32izalasr0p7 -menable-experimental-extensions -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-BADVERS %s
 // RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32izalasr0p7'
-// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.7 for experimental extension 'zalasr' (this compiler supports 0.1)
+// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.7 for experimental extension 'zalasr' (this compiler supports 0.9)
 
-// RUN: %clang --target=riscv32-unknown-elf -march=rv32izalasr0p1 -menable-experimental-extensions -### %s \
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izalasr0p9 -menable-experimental-extensions -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-GOODVERS %s
 // RV32-EXPERIMENTAL-GOODVERS: "-target-feature" "+experimental-zalasr"
 

clang/test/Preprocessor/riscv-target-features.c

@@ -1531,12 +1531,12 @@
 
 // Experimental extensions
 // RUN: %clang --target=riscv32 -menable-experimental-extensions \
-// RUN:   -march=rv32i_zalasr0p1 -E -dM %s \
+// RUN:   -march=rv32i_zalasr0p9 -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-ZALASR-EXT %s
 // RUN: %clang --target=riscv64 -menable-experimental-extensions \
-// RUN:   -march=rv64i_zalasr0p1 -E -dM %s \
+// RUN:   -march=rv64i_zalasr0p9 -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-ZALASR-EXT %s
-// CHECK-ZALASR-EXT: __riscv_zalasr 1000{{$}}
+// CHECK-ZALASR-EXT: __riscv_zalasr 9000{{$}}
 
 // RUN: %clang --target=riscv32 -menable-experimental-extensions \
 // RUN:   -march=rv32izfbfmin1p0 -E -dM %s \

compiler-rt/lib/builtins/cpu_model/aarch64/fmv/android.inc

@@ -27,8 +27,8 @@ void CONSTRUCTOR_ATTRIBUTE __init_cpu_features(void) {
 
   unsigned long hwcap = getauxval(AT_HWCAP);
   unsigned long hwcap2 = getauxval(AT_HWCAP2);
-  unsigned long hwcap2 = getauxval(AT_HWCAP3);
-  unsigned long hwcap2 = getauxval(AT_HWCAP4);
+  unsigned long hwcap3 = getauxval(AT_HWCAP3);
+  unsigned long hwcap4 = getauxval(AT_HWCAP4);
 
   __ifunc_arg_t arg;
   arg._size = sizeof(__ifunc_arg_t);

compiler-rt/lib/builtins/cpu_model/aarch64/fmv/getauxval.inc

@@ -12,8 +12,8 @@ void CONSTRUCTOR_ATTRIBUTE __init_cpu_features(void) {
 
   unsigned long hwcap = getauxval(AT_HWCAP);
   unsigned long hwcap2 = getauxval(AT_HWCAP2);
-  unsigned long hwcap2 = getauxval(AT_HWCAP3);
-  unsigned long hwcap2 = getauxval(AT_HWCAP4);
+  unsigned long hwcap3 = getauxval(AT_HWCAP3);
+  unsigned long hwcap4 = getauxval(AT_HWCAP4);
 
   __ifunc_arg_t arg;
   arg._size = sizeof(__ifunc_arg_t);

lldb/test/API/functionalities/unwind/cortex-m-exception/TestCortexMExceptionUnwind.py

@@ -12,21 +12,6 @@
 class TestCortexMExceptionUnwind(TestBase):
     NO_DEBUG_INFO_TESTCASE = True
 
-    # on the lldb-remote-linux-ubuntu CI, the binary.json's triple of
-    # armv7m-apple is not being set in the Target triple, and we're
-    # picking the wrong ABI plugin, ABISysV_arm.
-    # ABISysV_arm::CreateDefaultUnwindPlan() doesn't have a way to detect
-    # arm/thumb for a stack frame, or even the Target's triple for a
-    # Cortex-M part that is always thumb.  It hardcodes r11 as the frame
-    # pointer register, which is correct for arm code but not thumb.
-    # It is never correct # on a Cortex-M target.
-    # The Darwin ABIMacOSX_arm diverges from AAPCS and always uses r7 for
-    # the frame pointer -- the thumb convention -- whether executing arm or
-    # thumb.  So its CreateDefaultUnwindPlan picks the correct register for
-    # the frame pointer, and we can walk the stack.
-    # ABISysV_arm::CreateDefaultUnwindPlan will only get one frame and
-    # not be able to continue.
-    @skipIfRemote
     def test_no_fpu(self):
         """Test that we can backtrace correctly through an ARM Cortex-M Exception return stack"""
 
@@ -59,9 +44,8 @@ def test_no_fpu(self):
         # frames above that.  The topmost two stack frames
         # were not interesting for this test, so I didn't
         # create symbols for them.
-        self.assertEqual(thread.GetNumFrames(), 6)
+        self.assertEqual(thread.GetNumFrames(), 3)
         stackframe_names = [
-            "exception_catcher",
             "exception_catcher",
             "exception_thrower",
             "main",

lldb/test/API/functionalities/unwind/cortex-m-exception/armv7m-nofpu-exception.yaml

@@ -2,8 +2,8 @@ cpu: armv7m
 threads:
   - regsets:
       - flavor: gpr
-        registers: [{name: sp, value: 0x2000fe70}, {name: r7, value: 0x2000fe80}, 
-                    {name: pc, value: 0x0020392c}, {name: lr, value: 0x0020392d}]
+        registers: [{name: sp, value: 0x2000fe88}, {name: r7, value: 0x2000fe88}, 
+                    {name: pc, value: 0x00203916}, {name: lr, value: 0x0020392d}]
 memory-regions:
   # stack memory fetched via 
   # (lldb) p/x $sp
@@ -14,7 +14,7 @@ memory-regions:
       0x0000002a, 0x20010e58, 0x00203923, 0x00000001,
       0x2000fe88, 0x00203911, 0x2000ffdc, 0xfffffff9,
       0x00000102, 0x00000002, 0x000003f0, 0x0000002a,
-      0x20012620, 0x00203215, 0x00203366, 0x81000200,
+      0x20012620, 0x00203215, 0x00202a92, 0x81000200,
       0x00203215, 0x200128b0, 0x0024928d, 0x2000fecc,
       0x002491ed, 0x20010e58, 0x20010e4c, 0x2000ffa0,
       0x200107a0, 0x0000003c, 0x200116e8, 0x200108b0,
@@ -62,3 +62,26 @@ memory-regions:
       0x98, 0xae, 0x28, 0x00
     ]
 
+  # exception_thrower
+  # (lldb) disass -b -c 12 -n exception_thrower
+  # 0x202a88 <+0>:  0xb5f0       push   {r4, r5, r6, r7, lr}
+  # 0x202a8a <+2>:  0xaf03       add    r7, sp, #0xc
+  # 0x202a8c <+4>:  0xe92d0f00   push.w {r8, r9, r10, r11}
+  # 0x202a90 <+8>:  0xb0c3       sub    sp, #0x10c
+  # 0x202a92 <+10>: 0xf7ffffd9   bl     0x202a48                 
+  - addr: 0x202a88
+    UInt8: [
+      0xf0, 0xb5, 0x03, 0xaf, 0x2d, 0xe9, 0x00, 0x0f,
+      0xc3, 0xb0, 0xff, 0xf7, 0xd9, 0xff, 0xff, 0xf7
+    ]
+
+  # main:
+  # 0x202a7e <+0>: push   {r7, lr}
+  # 0x202a80 <+2>: mov    r7, sp
+  # 0x202a82 <+4>: bl     0x202a88                  ; exception_thrower
+  # 0x202a86 <+8>: nop
+  - addr: 0x202a7e
+    UInt8: [
+      0x80, 0xb5, 0x6f, 0x46, 0x00, 0xf0, 0x01, 0xf8,
+      0x00, 0xbf
+    ]

lldb/test/API/functionalities/unwind/cortex-m-exception/binary.json

@@ -1,5 +1,5 @@
 {
-  "triple": "armv7m-apple",
+  "triple": "armv7m--",
   "uuid": "2D157DBA-53C9-3AC7-B5A1-9D336EC831CB",
   "type": "executable",
   "sections": [
@@ -28,13 +28,13 @@
     {
       "name": "exception_catcher",
       "type": "code",
-      "size": 44,
+      "size": 32,
       "address": 2111760
     },
     {
       "name": "exception_thrower",
       "type": "code",
-      "size": 2652,
+      "size": 16,
       "address": 2108040
     }
   ]

llvm/docs/RISCVUsage.rst

@@ -334,7 +334,7 @@ LLVM supports (to various degrees) a number of experimental extensions.  All exp
 The primary goal of experimental support is to assist in the process of ratification by providing an existence proof of an implementation, and simplifying efforts to validate the value of a proposed extension against large code bases.  Experimental extensions are expected to either transition to ratified status, or be eventually removed.  The decision on whether to accept an experimental extension is currently done on an entirely case by case basis; if you want to propose one, attending the bi-weekly RISC-V sync-up call is strongly advised.
 
 ``experimental-zalasr``
-  LLVM implements the `0.0.5 draft specification <https://github.com/mehnadnerd/riscv-zalasr>`__.
+  LLVM implements the `0.9 draft specification <https://github.com/riscv/riscv-zalasr/releases/tag/v0.9>`__.
 
 ``experimental-zibi``
   LLVM implements the `0.1 release specification <https://github.com/riscv/zibi/releases/tag/v0.1.0>`__.