Skip to content

Commit 769e1c5

Browse files
topperctopperc
committed
[RISCV] Rename operands used for branch and compressed jump targets. NFC
The current names look just like predicates we use for regular immediates, but branches and jumps also allow bare symbols. While I was there I realized I could use PredicateMethod to have the AsmMatcher directly call the template function we use in the asm parser.
1 parent 0ed4bdf commit 769e1c5

File tree

5 files changed

+60
-62
lines changed

5 files changed

+60
-62
lines changed

‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp‎

Lines changed: 4 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -967,8 +967,6 @@ struct RISCVOperand final : public MCParsedAsmOperand {
967967
VK == RISCVMCExpr::VK_None;
968968
}
969969

970-
bool isSImm9Lsb0() const { return isBareSimmNLsb0<9>(); }
971-
972970
bool isUImm9Lsb000() const {
973971
if (!isImm())
974972
return false;
@@ -1026,8 +1024,6 @@ struct RISCVOperand final : public MCParsedAsmOperand {
10261024
VK == RISCVMCExpr::VK_TLSDESC_ADD_LO);
10271025
}
10281026

1029-
bool isSImm12Lsb0() const { return isBareSimmNLsb0<12>(); }
1030-
10311027
bool isSImm12Lsb00000() const {
10321028
if (!isImm())
10331029
return false;
@@ -1039,8 +1035,6 @@ struct RISCVOperand final : public MCParsedAsmOperand {
10391035
VK == RISCVMCExpr::VK_None;
10401036
}
10411037

1042-
bool isSImm13Lsb0() const { return isBareSimmNLsb0<13>(); }
1043-
10441038
bool isSImm10Lsb0000NonZero() const {
10451039
if (!isImm())
10461040
return false;
@@ -1114,8 +1108,6 @@ struct RISCVOperand final : public MCParsedAsmOperand {
11141108
VK == RISCVMCExpr::VK_TLSDESC_HI);
11151109
}
11161110

1117-
bool isSImm21Lsb0JAL() const { return isBareSimmNLsb0<21>(); }
1118-
11191111
bool isImmZero() const {
11201112
if (!isImm())
11211113
return false;
@@ -1728,7 +1720,7 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
17281720
return generateImmOutOfRangeError(
17291721
Operands, ErrorInfo, 0, (1 << 8) - 8,
17301722
"immediate must be a multiple of 8 bytes in the range");
1731-
case Match_InvalidSImm9Lsb0:
1723+
case Match_InvalidBareSImm9Lsb0:
17321724
return generateImmOutOfRangeError(
17331725
Operands, ErrorInfo, -(1 << 8), (1 << 8) - 2,
17341726
"immediate must be a multiple of 2 bytes in the range");
@@ -1758,15 +1750,15 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
17581750
Operands, ErrorInfo, -(1 << 11), (1 << 11) - 1,
17591751
"operand must be a symbol with %lo/%pcrel_lo/%tprel_lo specifier or an "
17601752
"integer in the range");
1761-
case Match_InvalidSImm12Lsb0:
1753+
case Match_InvalidBareSImm12Lsb0:
17621754
return generateImmOutOfRangeError(
17631755
Operands, ErrorInfo, -(1 << 11), (1 << 11) - 2,
17641756
"immediate must be a multiple of 2 bytes in the range");
17651757
case Match_InvalidSImm12Lsb00000:
17661758
return generateImmOutOfRangeError(
17671759
Operands, ErrorInfo, -(1 << 11), (1 << 11) - 32,
17681760
"immediate must be a multiple of 32 bytes in the range");
1769-
case Match_InvalidSImm13Lsb0:
1761+
case Match_InvalidBareSImm13Lsb0:
17701762
return generateImmOutOfRangeError(
17711763
Operands, ErrorInfo, -(1 << 12), (1 << 12) - 2,
17721764
"immediate must be a multiple of 2 bytes in the range");
@@ -1789,7 +1781,7 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
17891781
"%pcrel_hi/%got_pcrel_hi/%tls_ie_pcrel_hi/%tls_gd_pcrel_hi specifier "
17901782
"or "
17911783
"an integer in the range");
1792-
case Match_InvalidSImm21Lsb0JAL:
1784+
case Match_InvalidBareSImm21Lsb0:
17931785
return generateImmOutOfRangeError(
17941786
Operands, ErrorInfo, -(1 << 20), (1 << 20) - 2,
17951787
"immediate must be a multiple of 2 bytes in the range");

‎llvm/lib/Target/RISCV/RISCVInstrInfo.td‎

Lines changed: 24 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -161,6 +161,11 @@ class UImmAsmOperand<int width, string suffix = "">
161161
: ImmAsmOperand<"U", width, suffix> {
162162
}
163163

164+
class BareSImmNLsb0AsmOperand<int width>
165+
: ImmAsmOperand<"BareS", width, "Lsb0"> {
166+
let PredicateMethod = "isBareSimmNLsb0<" # width # ">";
167+
}
168+
164169
class RISCVOp<ValueType vt = XLenVT> : Operand<vt> {
165170
let OperandNamespace = "RISCVOp";
166171
}
@@ -271,8 +276,8 @@ def simm12_no6 : ImmLeaf<XLenVT, [{
271276
return isInt<12>(Imm) && !isInt<6>(Imm) && isInt<12>(-Imm);}]>;
272277

273278
// A 13-bit signed immediate where the least significant bit is zero.
274-
def simm13_lsb0 : Operand<OtherVT> {
275-
let ParserMatchClass = SImmAsmOperand<13, "Lsb0">;
279+
def bare_simm13_lsb0 : Operand<OtherVT> {
280+
let ParserMatchClass = BareSImmNLsb0AsmOperand<13>;
276281
let PrintMethod = "printBranchOperand";
277282
let EncoderMethod = "getImmOpValueAsr1";
278283
let DecoderMethod = "decodeSImmOperandAndLsl1<13>";
@@ -303,7 +308,7 @@ def uimm20_auipc : UImm20OperandMaybeSym {
303308

304309
def uimm20 : RISCVUImmOp<20>;
305310

306-
def Simm21Lsb0JALAsmOperand : SImmAsmOperand<21, "Lsb0JAL"> {
311+
def Simm21Lsb0JALAsmOperand : BareSImmNLsb0AsmOperand<21> {
307312
let ParserMethod = "parseJALOffset";
308313
}
309314

@@ -527,7 +532,7 @@ include "RISCVInstrFormatsV.td"
527532

528533
class BranchCC_rri<bits<3> funct3, string opcodestr>
529534
: RVInstB<funct3, OPC_BRANCH, (outs),
530-
(ins GPR:$rs1, GPR:$rs2, simm13_lsb0:$imm12),
535+
(ins GPR:$rs1, GPR:$rs2, bare_simm13_lsb0:$imm12),
531536
opcodestr, "$rs1, $rs2, $imm12">,
532537
Sched<[WriteJmp, ReadJmp, ReadJmp]> {
533538
let isBranch = 1;
@@ -959,30 +964,30 @@ def : InstAlias<"sgt $rd, $rs, $rt", (SLT GPR:$rd, GPR:$rt, GPR:$rs), 0>;
959964
def : InstAlias<"sgtu $rd, $rs, $rt", (SLTU GPR:$rd, GPR:$rt, GPR:$rs), 0>;
960965

961966
def : InstAlias<"beqz $rs, $offset",
962-
(BEQ GPR:$rs, X0, simm13_lsb0:$offset)>;
967+
(BEQ GPR:$rs, X0, bare_simm13_lsb0:$offset)>;
963968
def : InstAlias<"bnez $rs, $offset",
964-
(BNE GPR:$rs, X0, simm13_lsb0:$offset)>;
969+
(BNE GPR:$rs, X0, bare_simm13_lsb0:$offset)>;
965970
def : InstAlias<"blez $rs, $offset",
966-
(BGE X0, GPR:$rs, simm13_lsb0:$offset)>;
971+
(BGE X0, GPR:$rs, bare_simm13_lsb0:$offset)>;
967972
def : InstAlias<"bgez $rs, $offset",
968-
(BGE GPR:$rs, X0, simm13_lsb0:$offset)>;
973+
(BGE GPR:$rs, X0, bare_simm13_lsb0:$offset)>;
969974
def : InstAlias<"bltz $rs, $offset",
970-
(BLT GPR:$rs, X0, simm13_lsb0:$offset)>;
975+
(BLT GPR:$rs, X0, bare_simm13_lsb0:$offset)>;
971976
def : InstAlias<"bgtz $rs, $offset",
972-
(BLT X0, GPR:$rs, simm13_lsb0:$offset)>;
977+
(BLT X0, GPR:$rs, bare_simm13_lsb0:$offset)>;
973978

974979
// Always output the canonical mnemonic for the pseudo branch instructions.
975980
// The GNU tools emit the canonical mnemonic for the branch pseudo instructions
976981
// as well (e.g. "bgt" will be recognised by the assembler but never printed by
977982
// objdump). Match this behaviour by setting a zero weight.
978983
def : InstAlias<"bgt $rs, $rt, $offset",
979-
(BLT GPR:$rt, GPR:$rs, simm13_lsb0:$offset), 0>;
984+
(BLT GPR:$rt, GPR:$rs, bare_simm13_lsb0:$offset), 0>;
980985
def : InstAlias<"ble $rs, $rt, $offset",
981-
(BGE GPR:$rt, GPR:$rs, simm13_lsb0:$offset), 0>;
986+
(BGE GPR:$rt, GPR:$rs, bare_simm13_lsb0:$offset), 0>;
982987
def : InstAlias<"bgtu $rs, $rt, $offset",
983-
(BLTU GPR:$rt, GPR:$rs, simm13_lsb0:$offset), 0>;
988+
(BLTU GPR:$rt, GPR:$rs, bare_simm13_lsb0:$offset), 0>;
984989
def : InstAlias<"bleu $rs, $rt, $offset",
985-
(BGEU GPR:$rt, GPR:$rs, simm13_lsb0:$offset), 0>;
990+
(BGEU GPR:$rt, GPR:$rs, bare_simm13_lsb0:$offset), 0>;
986991

987992
def : InstAlias<"j $offset", (JAL X0, simm21_lsb0_jal:$offset)>;
988993
def : InstAlias<"jal $offset", (JAL X1, simm21_lsb0_jal:$offset)>;
@@ -1165,7 +1170,7 @@ def InsnI_Mem : DirectiveInsnI<(outs AnyReg:$rd), (ins uimm7_opcode:$opcode,
11651170
"$opcode, $funct3, $rd, ${imm12}(${rs1})">;
11661171
def InsnB : DirectiveInsnB<(outs), (ins uimm7_opcode:$opcode, uimm3:$funct3,
11671172
AnyReg:$rs1, AnyReg:$rs2,
1168-
simm13_lsb0:$imm12),
1173+
bare_simm13_lsb0:$imm12),
11691174
"$opcode, $funct3, $rs1, $rs2, $imm12">;
11701175
def InsnU : DirectiveInsnU<(outs AnyReg:$rd), (ins uimm7_opcode:$opcode,
11711176
uimm20_lui:$imm20),
@@ -1221,11 +1226,11 @@ def : InstAlias<".insn_i $opcode, $funct3, $rd, (${rs1})",
12211226
AnyReg:$rs1, 0)>;
12221227
def : InstAlias<".insn_b $opcode, $funct3, $rs1, $rs2, $imm12",
12231228
(InsnB uimm7_opcode:$opcode, uimm3:$funct3, AnyReg:$rs1,
1224-
AnyReg:$rs2, simm13_lsb0:$imm12)>;
1229+
AnyReg:$rs2, bare_simm13_lsb0:$imm12)>;
12251230
// Accept sb as an alias for b.
12261231
def : InstAlias<".insn_sb $opcode, $funct3, $rs1, $rs2, $imm12",
12271232
(InsnB uimm7_opcode:$opcode, uimm3:$funct3, AnyReg:$rs1,
1228-
AnyReg:$rs2, simm13_lsb0:$imm12)>;
1233+
AnyReg:$rs2, bare_simm13_lsb0:$imm12)>;
12291234
def : InstAlias<".insn_u $opcode, $rd, $imm20",
12301235
(InsnU AnyReg:$rd, uimm7_opcode:$opcode, uimm20_lui:$imm20)>;
12311236
def : InstAlias<".insn_j $opcode, $rd, $imm20",
@@ -1571,10 +1576,10 @@ let Predicates = [HasStdExtC, OptForMinSize] in {
15711576
// Match `riscv_brcc` and lower to the appropriate RISC-V branch instruction.
15721577
multiclass BccPat<CondCode Cond, RVInstB Inst> {
15731578
def : Pat<(riscv_brcc (XLenVT GPR:$rs1), GPR:$rs2, Cond, bb:$imm12),
1574-
(Inst GPR:$rs1, GPR:$rs2, simm13_lsb0:$imm12)>;
1579+
(Inst GPR:$rs1, GPR:$rs2, bare_simm13_lsb0:$imm12)>;
15751580
// Explicitly select 0 to X0. The register coalescer doesn't always do it.
15761581
def : Pat<(riscv_brcc (XLenVT GPR:$rs1), 0, Cond, bb:$imm12),
1577-
(Inst GPR:$rs1, (XLenVT X0), simm13_lsb0:$imm12)>;
1582+
(Inst GPR:$rs1, (XLenVT X0), bare_simm13_lsb0:$imm12)>;
15781583
}
15791584

15801585
class BrccCompressOpt<CondCode Cond, RVInstB Inst>

‎llvm/lib/Target/RISCV/RISCVInstrInfoC.td‎

Lines changed: 25 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -138,9 +138,9 @@ def uimm8_lsb000 : RISCVOp,
138138
}
139139

140140
// A 9-bit signed immediate where the least significant bit is zero.
141-
def simm9_lsb0 : Operand<OtherVT>,
142-
ImmLeaf<XLenVT, [{return isShiftedInt<8, 1>(Imm);}]> {
143-
let ParserMatchClass = SImmAsmOperand<9, "Lsb0">;
141+
def bare_simm9_lsb0 : Operand<OtherVT>,
142+
ImmLeaf<XLenVT, [{return isShiftedInt<8, 1>(Imm);}]> {
143+
let ParserMatchClass = BareSImmNLsb0AsmOperand<9>;
144144
let PrintMethod = "printBranchOperand";
145145
let EncoderMethod = "getImmOpValueAsr1";
146146
let DecoderMethod = "decodeSImmOperandAndLsl1<9>";
@@ -202,9 +202,9 @@ def simm10_lsb0000nonzero : RISCVOp,
202202
}
203203

204204
// A 12-bit signed immediate where the least significant bit is zero.
205-
def simm12_lsb0 : Operand<XLenVT>,
206-
ImmLeaf<XLenVT, [{return isShiftedInt<11, 1>(Imm);}]> {
207-
let ParserMatchClass = SImmAsmOperand<12, "Lsb0">;
205+
def bare_simm12_lsb0 : Operand<OtherVT>,
206+
ImmLeaf<XLenVT, [{return isShiftedInt<11, 1>(Imm);}]> {
207+
let ParserMatchClass = BareSImmNLsb0AsmOperand<12>;
208208
let PrintMethod = "printBranchOperand";
209209
let EncoderMethod = "getImmOpValueAsr1";
210210
let DecoderMethod = "decodeSImmOperandAndLsl1<12>";
@@ -258,7 +258,7 @@ class CStore_rri<bits<3> funct3, string OpcodeStr,
258258

259259
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
260260
class Bcz<bits<3> funct3, string OpcodeStr>
261-
: RVInst16CB<funct3, 0b01, (outs), (ins GPRC:$rs1, simm9_lsb0:$imm),
261+
: RVInst16CB<funct3, 0b01, (outs), (ins GPRC:$rs1, bare_simm9_lsb0:$imm),
262262
OpcodeStr, "$rs1, $imm"> {
263263
let isBranch = 1;
264264
let isTerminator = 1;
@@ -417,7 +417,7 @@ def PseudoC_ADDI_NOP : Pseudo<(outs GPRX0:$rd), (ins GPRX0:$rs1, immzero:$imm),
417417
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCall = 1,
418418
DecoderNamespace = "RV32Only", Defs = [X1],
419419
Predicates = [HasStdExtCOrZca, IsRV32] in
420-
def C_JAL : RVInst16CJ<0b001, 0b01, (outs), (ins simm12_lsb0:$offset),
420+
def C_JAL : RVInst16CJ<0b001, 0b01, (outs), (ins bare_simm12_lsb0:$offset),
421421
"c.jal", "$offset">, Sched<[WriteJal]>;
422422

423423
let hasSideEffects = 0, mayLoad = 0, mayStore = 0,
@@ -486,7 +486,7 @@ def C_ADDW : CA_ALU<0b100111, 0b01, "c.addw">,
486486
}
487487

488488
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
489-
def C_J : RVInst16CJ<0b101, 0b01, (outs), (ins simm12_lsb0:$offset),
489+
def C_J : RVInst16CJ<0b101, 0b01, (outs), (ins bare_simm12_lsb0:$offset),
490490
"c.j", "$offset">, Sched<[WriteJmp]> {
491491
let isBranch = 1;
492492
let isTerminator=1;
@@ -793,11 +793,11 @@ def InsnCA : DirectiveInsnCA<(outs AnyRegC:$rd), (ins uimm2_opcode:$opcode,
793793
"$opcode, $funct6, $funct2, $rd, $rs2">;
794794
def InsnCB : DirectiveInsnCB<(outs), (ins uimm2_opcode:$opcode, uimm3:$funct3,
795795
AnyRegC:$rs1,
796-
simm9_lsb0:$imm8),
796+
bare_simm9_lsb0:$imm8),
797797
"$opcode, $funct3, $rs1, $imm8">;
798798
def InsnCJ : DirectiveInsnCJ<(outs), (ins uimm2_opcode:$opcode,
799799
uimm3:$funct3,
800-
simm12_lsb0:$imm11),
800+
bare_simm12_lsb0:$imm11),
801801
"$opcode, $funct3, $imm11">;
802802
def Insn16 : RVInst16<(outs), (ins uimm16:$value), "", "", [], InstFormatOther> {
803803
bits<16> value;
@@ -841,9 +841,9 @@ def : InstAlias<".insn_ca $opcode, $funct6, $funct2, $rd, $rs2",
841841
uimm2:$funct2, AnyRegC:$rs2)>;
842842
def : InstAlias<".insn_cb $opcode, $funct3, $rs1, $imm8",
843843
(InsnCB uimm2_opcode:$opcode, uimm3:$funct3, AnyRegC:$rs1,
844-
simm9_lsb0:$imm8)>;
844+
bare_simm9_lsb0:$imm8)>;
845845
def : InstAlias<".insn_cj $opcode, $funct3, $imm11",
846-
(InsnCJ uimm2_opcode:$opcode, uimm3:$funct3, simm12_lsb0:$imm11)>;
846+
(InsnCJ uimm2_opcode:$opcode, uimm3:$funct3, bare_simm12_lsb0:$imm11)>;
847847
}
848848

849849
//===----------------------------------------------------------------------===/i
@@ -915,8 +915,8 @@ def : CompressPat<(ADDI GPRNoX0:$rs1, GPRNoX0:$rs1, simm6nonzero:$imm),
915915
} // Predicates = [HasStdExtCOrZca]
916916

917917
let Predicates = [HasStdExtCOrZca, IsRV32] in {
918-
def : CompressPat<(JAL X1, simm12_lsb0:$offset),
919-
(C_JAL simm12_lsb0:$offset)>;
918+
def : CompressPat<(JAL X1, bare_simm12_lsb0:$offset),
919+
(C_JAL bare_simm12_lsb0:$offset)>;
920920
} // Predicates = [HasStdExtCOrZca, IsRV32]
921921

922922
let Predicates = [HasStdExtCOrZca, IsRV64] in {
@@ -970,18 +970,18 @@ def : CompressPat<(ADDW GPRC:$rs1, GPRC:$rs2, GPRC:$rs1),
970970
} // Predicates = [HasStdExtCOrZca, IsRV64]
971971

972972
let Predicates = [HasStdExtCOrZca] in {
973-
def : CompressPat<(JAL X0, simm12_lsb0:$offset),
974-
(C_J simm12_lsb0:$offset)>;
975-
def : CompressPat<(BEQ GPRC:$rs1, X0, simm9_lsb0:$imm),
976-
(C_BEQZ GPRC:$rs1, simm9_lsb0:$imm)>;
973+
def : CompressPat<(JAL X0, bare_simm12_lsb0:$offset),
974+
(C_J bare_simm12_lsb0:$offset)>;
975+
def : CompressPat<(BEQ GPRC:$rs1, X0, bare_simm9_lsb0:$imm),
976+
(C_BEQZ GPRC:$rs1, bare_simm9_lsb0:$imm)>;
977977
let isCompressOnly = true in
978-
def : CompressPat<(BEQ X0, GPRC:$rs1, simm9_lsb0:$imm),
979-
(C_BEQZ GPRC:$rs1, simm9_lsb0:$imm)>;
980-
def : CompressPat<(BNE GPRC:$rs1, X0, simm9_lsb0:$imm),
981-
(C_BNEZ GPRC:$rs1, simm9_lsb0:$imm)>;
978+
def : CompressPat<(BEQ X0, GPRC:$rs1, bare_simm9_lsb0:$imm),
979+
(C_BEQZ GPRC:$rs1, bare_simm9_lsb0:$imm)>;
980+
def : CompressPat<(BNE GPRC:$rs1, X0, bare_simm9_lsb0:$imm),
981+
(C_BNEZ GPRC:$rs1, bare_simm9_lsb0:$imm)>;
982982
let isCompressOnly = true in
983-
def : CompressPat<(BNE X0, GPRC:$rs1, simm9_lsb0:$imm),
984-
(C_BNEZ GPRC:$rs1, simm9_lsb0:$imm)>;
983+
def : CompressPat<(BNE X0, GPRC:$rs1, bare_simm9_lsb0:$imm),
984+
(C_BNEZ GPRC:$rs1, bare_simm9_lsb0:$imm)>;
985985
} // Predicates = [HasStdExtCOrZca]
986986

987987
// Quadrant 2

‎llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -590,10 +590,10 @@ let Predicates = [HasVendorXCVsimd, IsRV32] in {
590590
let Predicates = [HasVendorXCVbi, IsRV32] in {
591591
// Immediate branching operations
592592
def CV_BEQIMM : CVInstImmBranch<0b110, (outs),
593-
(ins GPR:$rs1, simm5:$imm5, simm13_lsb0:$imm12),
593+
(ins GPR:$rs1, simm5:$imm5, bare_simm13_lsb0:$imm12),
594594
"cv.beqimm", "$rs1, $imm5, $imm12">, Sched<[]>;
595595
def CV_BNEIMM : CVInstImmBranch<0b111, (outs),
596-
(ins GPR:$rs1, simm5:$imm5, simm13_lsb0:$imm12),
596+
(ins GPR:$rs1, simm5:$imm5, bare_simm13_lsb0:$imm12),
597597
"cv.bneimm", "$rs1, $imm5, $imm12">, Sched<[]>;
598598
}
599599

@@ -793,9 +793,9 @@ let Predicates = [HasVendorXCValu, IsRV32], AddedComplexity = 1 in {
793793

794794
let Predicates = [HasVendorXCVbi, IsRV32], AddedComplexity = 2 in {
795795
def : Pat<(riscv_brcc GPR:$rs1, simm5:$imm5, SETEQ, bb:$imm12),
796-
(CV_BEQIMM GPR:$rs1, simm5:$imm5, simm13_lsb0:$imm12)>;
796+
(CV_BEQIMM GPR:$rs1, simm5:$imm5, bare_simm13_lsb0:$imm12)>;
797797
def : Pat<(riscv_brcc GPR:$rs1, simm5:$imm5, SETNE, bb:$imm12),
798-
(CV_BNEIMM GPR:$rs1, simm5:$imm5, simm13_lsb0:$imm12)>;
798+
(CV_BNEIMM GPR:$rs1, simm5:$imm5, bare_simm13_lsb0:$imm12)>;
799799

800800
let usesCustomInserter = 1 in
801801
def Select_GPR_Using_CC_Imm : Pseudo<(outs GPR:$dst),

‎llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -314,7 +314,7 @@ class QCIRVInst16CI_RS1<bits<5> funct5, string OpcodeStr>
314314

315315
class QCIBranchInst_rii<bits<3> funct3, DAGOperand InTyImm5, string opcodestr>
316316
: RVInstB<funct3, OPC_CUSTOM_3, (outs),
317-
(ins GPRNoX0:$rs1, InTyImm5:$rs2, simm13_lsb0:$imm12),
317+
(ins GPRNoX0:$rs1, InTyImm5:$rs2, bare_simm13_lsb0:$imm12),
318318
opcodestr, "$rs1, $rs2, $imm12"> {
319319
let isBranch = 1;
320320
let isTerminator = 1;
@@ -324,7 +324,8 @@ class QCIBranchInst_rii<bits<3> funct3, DAGOperand InTyImm5, string opcodestr>
324324
}
325325

326326
class QCIBranchInst48_rii<bits<5> funct5, DAGOperand InTyImm16, string opcodestr>
327-
: RVInst48<(outs), (ins GPRNoX0:$rs1, InTyImm16:$imm16, simm13_lsb0:$imm12),
327+
: RVInst48<(outs),
328+
(ins GPRNoX0:$rs1, InTyImm16:$imm16, bare_simm13_lsb0:$imm12),
328329
opcodestr, "$rs1, $imm16, $imm12", [], InstFormatOther> {
329330
bits<5> rs1;
330331
bits<16> imm16;

0 commit comments

Comments
 (0)