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folkertdevfolkertdev
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s390x: legalize smin/smax/umin/umax for v128q
1 parent 832f1f9 commit 76bf0f3

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4 files changed

+23
-20
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4 files changed

+23
-20
lines changed

‎llvm/lib/Target/SystemZ/SystemZISelLowering.cpp‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -287,6 +287,9 @@ SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
287287
// Additional instructions available with z17.
288288
if (Subtarget.hasVectorEnhancements3()) {
289289
setOperationAction(ISD::ABS, MVT::i128, Legal);
290+
291+
setOperationAction({ISD::SMIN, ISD::UMIN, ISD::SMAX, ISD::UMAX},
292+
MVT::i128, Legal);
290293
}
291294
}
292295

‎llvm/lib/Target/SystemZ/SystemZInstrVector.td‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -685,7 +685,7 @@ let Predicates = [FeatureVector] in {
685685
def VMXF : BinaryVRRc<"vmxf", 0xE7FF, smax, v128f, v128f, 2>;
686686
def VMXG : BinaryVRRc<"vmxg", 0xE7FF, smax, v128g, v128g, 3>;
687687
let Predicates = [FeatureVectorEnhancements3] in
688-
def VMXQ : BinaryVRRc<"vmxq", 0xE7FF, null_frag, v128q, v128q, 4>;
688+
def VMXQ : BinaryVRRc<"vmxq", 0xE7FF, smax, v128q, v128q, 4>;
689689

690690
// Maximum logical.
691691
def VMXL : BinaryVRRcGeneric<"vmxl", 0xE7FD>;
@@ -694,7 +694,7 @@ let Predicates = [FeatureVector] in {
694694
def VMXLF : BinaryVRRc<"vmxlf", 0xE7FD, umax, v128f, v128f, 2>;
695695
def VMXLG : BinaryVRRc<"vmxlg", 0xE7FD, umax, v128g, v128g, 3>;
696696
let Predicates = [FeatureVectorEnhancements3] in
697-
def VMXLQ : BinaryVRRc<"vmxlq", 0xE7FD, null_frag, v128q, v128q, 4>;
697+
def VMXLQ : BinaryVRRc<"vmxlq", 0xE7FD, umax, v128q, v128q, 4>;
698698
}
699699

700700
let isCommutable = 1 in {
@@ -705,7 +705,7 @@ let Predicates = [FeatureVector] in {
705705
def VMNF : BinaryVRRc<"vmnf", 0xE7FE, smin, v128f, v128f, 2>;
706706
def VMNG : BinaryVRRc<"vmng", 0xE7FE, smin, v128g, v128g, 3>;
707707
let Predicates = [FeatureVectorEnhancements3] in
708-
def VMNQ : BinaryVRRc<"vmnq", 0xE7FE, null_frag, v128q, v128q, 4>;
708+
def VMNQ : BinaryVRRc<"vmnq", 0xE7FE, smin, v128q, v128q, 4>;
709709

710710
// Minimum logical.
711711
def VMNL : BinaryVRRcGeneric<"vmnl", 0xE7FC>;
@@ -714,7 +714,7 @@ let Predicates = [FeatureVector] in {
714714
def VMNLF : BinaryVRRc<"vmnlf", 0xE7FC, umin, v128f, v128f, 2>;
715715
def VMNLG : BinaryVRRc<"vmnlg", 0xE7FC, umin, v128g, v128g, 3>;
716716
let Predicates = [FeatureVectorEnhancements3] in
717-
def VMNLQ : BinaryVRRc<"vmnlq", 0xE7FC, null_frag, v128q, v128q, 4>;
717+
def VMNLQ : BinaryVRRc<"vmnlq", 0xE7FC, umin, v128q, v128q, 4>;
718718
}
719719

720720
let isCommutable = 1 in {

‎llvm/test/CodeGen/SystemZ/int-max-02.ll‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -7,8 +7,8 @@
77
define i128 @f1(i128 %val1, i128 %val2) {
88
; CHECK-LABEL: f1:
99
; CHECK: # %bb.0:
10-
; CHECK-NEXT: vl %v0, 0(%r3), 3
11-
; CHECK-NEXT: vl %v1, 0(%r4), 3
10+
; CHECK-NEXT: vl %v0, 0(%r4), 3
11+
; CHECK-NEXT: vl %v1, 0(%r3), 3
1212
; CHECK-NEXT: vmxq %v0, %v1, %v0
1313
; CHECK-NEXT: vst %v0, 0(%r2), 3
1414
; CHECK-NEXT: br %r14
@@ -49,8 +49,8 @@ define i128 @f3(i128 %val1, i128 %val2) {
4949
define i128 @f4(i128 %val1, i128 %val2) {
5050
; CHECK-LABEL: f4:
5151
; CHECK: # %bb.0:
52-
; CHECK-NEXT: vl %v0, 0(%r3), 3
53-
; CHECK-NEXT: vl %v1, 0(%r4), 3
52+
; CHECK-NEXT: vl %v0, 0(%r4), 3
53+
; CHECK-NEXT: vl %v1, 0(%r3), 3
5454
; CHECK-NEXT: vmxq %v0, %v1, %v0
5555
; CHECK-NEXT: vst %v0, 0(%r2), 3
5656
; CHECK-NEXT: br %r14
@@ -63,8 +63,8 @@ define i128 @f4(i128 %val1, i128 %val2) {
6363
define i128 @f5(i128 %val1, i128 %val2) {
6464
; CHECK-LABEL: f5:
6565
; CHECK: # %bb.0:
66-
; CHECK-NEXT: vl %v0, 0(%r3), 3
67-
; CHECK-NEXT: vl %v1, 0(%r4), 3
66+
; CHECK-NEXT: vl %v0, 0(%r4), 3
67+
; CHECK-NEXT: vl %v1, 0(%r3), 3
6868
; CHECK-NEXT: vmxlq %v0, %v1, %v0
6969
; CHECK-NEXT: vst %v0, 0(%r2), 3
7070
; CHECK-NEXT: br %r14
@@ -105,8 +105,8 @@ define i128 @f7(i128 %val1, i128 %val2) {
105105
define i128 @f8(i128 %val1, i128 %val2) {
106106
; CHECK-LABEL: f8:
107107
; CHECK: # %bb.0:
108-
; CHECK-NEXT: vl %v0, 0(%r3), 3
109-
; CHECK-NEXT: vl %v1, 0(%r4), 3
108+
; CHECK-NEXT: vl %v0, 0(%r4), 3
109+
; CHECK-NEXT: vl %v1, 0(%r3), 3
110110
; CHECK-NEXT: vmxlq %v0, %v1, %v0
111111
; CHECK-NEXT: vst %v0, 0(%r2), 3
112112
; CHECK-NEXT: br %r14

‎llvm/test/CodeGen/SystemZ/int-min-02.ll‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -7,8 +7,8 @@
77
define i128 @f1(i128 %val1, i128 %val2) {
88
; CHECK-LABEL: f1:
99
; CHECK: # %bb.0:
10-
; CHECK-NEXT: vl %v0, 0(%r4), 3
11-
; CHECK-NEXT: vl %v1, 0(%r3), 3
10+
; CHECK-NEXT: vl %v0, 0(%r3), 3
11+
; CHECK-NEXT: vl %v1, 0(%r4), 3
1212
; CHECK-NEXT: vmnq %v0, %v1, %v0
1313
; CHECK-NEXT: vst %v0, 0(%r2), 3
1414
; CHECK-NEXT: br %r14
@@ -49,8 +49,8 @@ define i128 @f3(i128 %val1, i128 %val2) {
4949
define i128 @f4(i128 %val1, i128 %val2) {
5050
; CHECK-LABEL: f4:
5151
; CHECK: # %bb.0:
52-
; CHECK-NEXT: vl %v0, 0(%r4), 3
53-
; CHECK-NEXT: vl %v1, 0(%r3), 3
52+
; CHECK-NEXT: vl %v0, 0(%r3), 3
53+
; CHECK-NEXT: vl %v1, 0(%r4), 3
5454
; CHECK-NEXT: vmnq %v0, %v1, %v0
5555
; CHECK-NEXT: vst %v0, 0(%r2), 3
5656
; CHECK-NEXT: br %r14
@@ -63,8 +63,8 @@ define i128 @f4(i128 %val1, i128 %val2) {
6363
define i128 @f5(i128 %val1, i128 %val2) {
6464
; CHECK-LABEL: f5:
6565
; CHECK: # %bb.0:
66-
; CHECK-NEXT: vl %v0, 0(%r4), 3
67-
; CHECK-NEXT: vl %v1, 0(%r3), 3
66+
; CHECK-NEXT: vl %v0, 0(%r3), 3
67+
; CHECK-NEXT: vl %v1, 0(%r4), 3
6868
; CHECK-NEXT: vmnlq %v0, %v1, %v0
6969
; CHECK-NEXT: vst %v0, 0(%r2), 3
7070
; CHECK-NEXT: br %r14
@@ -105,8 +105,8 @@ define i128 @f7(i128 %val1, i128 %val2) {
105105
define i128 @f8(i128 %val1, i128 %val2) {
106106
; CHECK-LABEL: f8:
107107
; CHECK: # %bb.0:
108-
; CHECK-NEXT: vl %v0, 0(%r4), 3
109-
; CHECK-NEXT: vl %v1, 0(%r3), 3
108+
; CHECK-NEXT: vl %v0, 0(%r3), 3
109+
; CHECK-NEXT: vl %v1, 0(%r4), 3
110110
; CHECK-NEXT: vmnlq %v0, %v1, %v0
111111
; CHECK-NEXT: vst %v0, 0(%r2), 3
112112
; CHECK-NEXT: br %r14

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