update test

Author: broxigarchen

llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-vgpr16-to-spgr32.ll

@@ -1,10 +1,13 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck %s
 
+@lds = external local_unnamed_addr addrspace(3) global [4 x float], align 4
+
 ; expect readfirstlane to pick the 32bit register
-define amdgpu_gs i32 @vgpr16_copyto_sgpr(ptr addrspace(3) %a, i32 %b, ptr addrspace(1) %out) {
+define amdgpu_gs i32 @vgpr16_copyto_sgpr() {
 ; CHECK-LABEL: vgpr16_copyto_sgpr:
 ; CHECK:       ; %bb.0: ; %entry
+; CHECK-NEXT:    v_mov_b32_e32 v0, lds@abs32@lo
 ; CHECK-NEXT:    ds_load_2addr_b32 v[0:1], v0 offset1:1
 ; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
 ; CHECK-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
@@ -23,15 +26,15 @@ define amdgpu_gs i32 @vgpr16_copyto_sgpr(ptr addrspace(3) %a, i32 %b, ptr addrsp
 ; CHECK-NEXT:    s_branch .LBB0_3
 ; CHECK-NEXT:  .LBB0_3:
 entry:
-  %1 = load <4 x float>, ptr addrspace(3) poison, align 4
-  %2 = extractelement <4 x float> %1, i32 0
-  %3 = fptrunc float %2 to half
-  %4 = bitcast half %3 to i16
-  %5 = zext i16 %4 to i32
-  %6 = add i32 %5, 1
-  %7 = mul i32 %6, 5
-  %8 = icmp eq i32 %7, 7
-  br i1 %8, label %a1, label %a2
+  %ptr = load <4 x float>, ptr addrspace(3) @lds, align 4
+  %f = extractelement <4 x float> %ptr, i32 0
+  %half = fptrunc float %f to half
+  %i16 = bitcast half %half to i16
+  %i32 = zext i16 %i16 to i32
+  %add = add i32 %i32, 1
+  %mul = mul i32 %add, 5
+  %icmp = icmp eq i32 %mul, 7
+  br i1 %icmp, label %a1, label %a2
 
 a1:
   ret i32 1