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JulienVillette
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[MC] Account for AcquireAtCycle in getReciprocalThroughput (#132653)
Previously `MCSchedModel::getReciprocalThroughput` ignored `AcquireAtCycle` completey, this patch fixes it by using the largest `(ReleaseAtCycle - AcquireAtCycle) / NumUnits` as inverse throughput. Here are some technical explanations: https://myhsu.xyz/llvm-sched-interval-throughput --------- Co-authored-by: Julien Villette <[email protected]>
1 parent aa80388 commit 7764847

26 files changed

+836
-833
lines changed

‎llvm/lib/MC/MCSchedule.cpp‎

Lines changed: 9 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -96,19 +96,22 @@ int MCSchedModel::computeInstrLatency(const MCSubtargetInfo &STI,
9696
double
9797
MCSchedModel::getReciprocalThroughput(const MCSubtargetInfo &STI,
9898
const MCSchedClassDesc &SCDesc) {
99-
std::optional<double> Throughput;
99+
std::optional<double> MinThroughput;
100100
const MCSchedModel &SM = STI.getSchedModel();
101101
const MCWriteProcResEntry *I = STI.getWriteProcResBegin(&SCDesc);
102102
const MCWriteProcResEntry *E = STI.getWriteProcResEnd(&SCDesc);
103103
for (; I != E; ++I) {
104-
if (!I->ReleaseAtCycle)
104+
if (!I->ReleaseAtCycle || I->ReleaseAtCycle == I->AcquireAtCycle)
105105
continue;
106+
assert(I->ReleaseAtCycle > I->AcquireAtCycle && "invalid resource segment");
106107
unsigned NumUnits = SM.getProcResource(I->ProcResourceIdx)->NumUnits;
107-
double Temp = NumUnits * 1.0 / I->ReleaseAtCycle;
108-
Throughput = Throughput ? std::min(*Throughput, Temp) : Temp;
108+
double Throughput =
109+
double(NumUnits) / double(I->ReleaseAtCycle - I->AcquireAtCycle);
110+
MinThroughput =
111+
MinThroughput ? std::min(*MinThroughput, Throughput) : Throughput;
109112
}
110-
if (Throughput)
111-
return 1.0 / *Throughput;
113+
if (MinThroughput)
114+
return 1.0 / *MinThroughput;
112115

113116
// If no throughput value was calculated, assume that we can execute at the
114117
// maximum issue width scaled by number of micro-ops for the schedule class.

‎llvm/test/tools/llvm-mca/RISCV/SiFiveX280/different-lmul-instruments.s‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -28,9 +28,9 @@ vadd.vv v12, v12, v12
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2929
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
3030
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
31-
# CHECK-NEXT: 1 4 3.00 vadd.vv v12, v12, v12
31+
# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12
3232
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m8, tu, mu
33-
# CHECK-NEXT: 1 4 17.00 vadd.vv v12, v12, v12
33+
# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
3434

3535
# CHECK: Resources:
3636
# CHECK-NEXT: [0] - SiFive7FDiv

‎llvm/test/tools/llvm-mca/RISCV/SiFiveX280/different-sew-instruments.s‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -29,9 +29,9 @@ vdiv.vv v8, v8, v12
2929

3030
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
3131
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
32-
# CHECK-NEXT: 1 240 241.00 vdiv.vv v8, v8, v12
32+
# CHECK-NEXT: 1 240 240.00 vdiv.vv v8, v8, v12
3333
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e64, m1, tu, mu
34-
# CHECK-NEXT: 1 114 115.00 vdiv.vv v8, v8, v12
34+
# CHECK-NEXT: 1 114 114.00 vdiv.vv v8, v8, v12
3535

3636
# CHECK: Resources:
3737
# CHECK-NEXT: [0] - SiFive7FDiv

‎llvm/test/tools/llvm-mca/RISCV/SiFiveX280/disable-im.s‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -31,11 +31,11 @@ vadd.vv v12, v12, v12
3131

3232
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
3333
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m2, tu, mu
34-
# CHECK-NEXT: 1 4 17.00 vadd.vv v12, v12, v12
34+
# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
3535
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
36-
# CHECK-NEXT: 1 4 17.00 vadd.vv v12, v12, v12
36+
# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
3737
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m8, tu, mu
38-
# CHECK-NEXT: 1 4 17.00 vadd.vv v12, v12, v12
38+
# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
3939

4040
# CHECK: Resources:
4141
# CHECK-NEXT: [0] - SiFive7FDiv

‎llvm/test/tools/llvm-mca/RISCV/SiFiveX280/fractional-lmul-data.s‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -29,9 +29,9 @@ vdiv.vv v12, v12, v12
2929

3030
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
3131
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
32-
# CHECK-NEXT: 1 56 57.00 vdiv.vv v12, v12, v12
32+
# CHECK-NEXT: 1 56 56.00 vdiv.vv v12, v12, v12
3333
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
34-
# CHECK-NEXT: 1 30 31.00 vdiv.vv v12, v12, v12
34+
# CHECK-NEXT: 1 30 30.00 vdiv.vv v12, v12, v12
3535

3636
# CHECK: Resources:
3737
# CHECK-NEXT: [0] - SiFive7FDiv

‎llvm/test/tools/llvm-mca/RISCV/SiFiveX280/lmul-instrument-at-start.s‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,7 @@ vadd.vv v12, v12, v12
2525

2626
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
2727
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
28-
# CHECK-NEXT: 1 4 3.00 vadd.vv v12, v12, v12
28+
# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12
2929

3030
# CHECK: Resources:
3131
# CHECK-NEXT: [0] - SiFive7FDiv

‎llvm/test/tools/llvm-mca/RISCV/SiFiveX280/lmul-instrument-in-middle.s‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -25,9 +25,9 @@ vadd.vv v12, v12, v12
2525
# CHECK-NEXT: [6]: HasSideEffects (U)
2626

2727
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
28-
# CHECK-NEXT: 1 4 17.00 vadd.vv v12, v12, v12
28+
# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
2929
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, mf8, tu, mu
30-
# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12
30+
# CHECK-NEXT: 1 4 1.00 vadd.vv v12, v12, v12
3131

3232
# CHECK: Resources:
3333
# CHECK-NEXT: [0] - SiFive7FDiv

‎llvm/test/tools/llvm-mca/RISCV/SiFiveX280/lmul-instrument-in-region.s‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,7 @@ vadd.vv v12, v12, v12
2929

3030
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
3131
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
32-
# CHECK-NEXT: 1 4 3.00 vadd.vv v12, v12, v12
32+
# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12
3333

3434
# CHECK: Resources:
3535
# CHECK-NEXT: [0] - SiFive7FDiv

‎llvm/test/tools/llvm-mca/RISCV/SiFiveX280/lmul-instrument-straddles-region.s‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,7 @@ vadd.vv v12, v12, v12
3030

3131
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
3232
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
33-
# CHECK-NEXT: 1 4 3.00 vadd.vv v12, v12, v12
33+
# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12
3434

3535
# CHECK: Resources:
3636
# CHECK-NEXT: [0] - SiFive7FDiv

‎llvm/test/tools/llvm-mca/RISCV/SiFiveX280/multiple-same-lmul-instruments.s‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -33,13 +33,13 @@ vsub.vv v12, v12, v12
3333

3434
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
3535
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
36-
# CHECK-NEXT: 1 4 3.00 vadd.vv v12, v12, v12
36+
# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12
3737
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
38-
# CHECK-NEXT: 1 4 3.00 vadd.vv v12, v12, v12
39-
# CHECK-NEXT: 1 4 3.00 vsub.vv v12, v12, v12
38+
# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12
39+
# CHECK-NEXT: 1 4 2.00 vsub.vv v12, v12, v12
4040
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m4, tu, mu
41-
# CHECK-NEXT: 1 4 9.00 vadd.vv v12, v12, v12
42-
# CHECK-NEXT: 1 4 9.00 vsub.vv v12, v12, v12
41+
# CHECK-NEXT: 1 4 8.00 vadd.vv v12, v12, v12
42+
# CHECK-NEXT: 1 4 8.00 vsub.vv v12, v12, v12
4343

4444
# CHECK: Resources:
4545
# CHECK-NEXT: [0] - SiFive7FDiv

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